# Makefile for cocotb

# defaults
SIM ?= icarus
TOPLEVEL_LANG ?= verilog

VERILOG_SOURCES ?= $(PWD)/../src/video_double_buffer_16bit.v
VERILOG_SOURCES += $(PWD)/../src/video_fifo/video_packet_sender_2.v
VERILOG_SOURCES += $(PWD)/test_yuy2.v

# use VHDL_SOURCES for VHDL files

# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL = test_yuy2

# MODULE is the basename of the Python test file
MODULE = both_fifo_sender_tb

# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim