<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW5A-25A" pn="GW5A-LV25MG121NES">gw5a25a-000</Device>
    <FileList>
        <File path="src/MIPI_CSI_HardPhy_Rx.v" type="file.verilog" enable="1"/>
        <File path="src/MIPI_CSI_SoftPhy_Rx.v" type="file.verilog" enable="1"/>
        <File path="src/byte_to_pixel/byte_to_pixel.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/huff_fifo_sc_afull/huff_fifo_sc_afull.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/img_fifo.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/img_fifo_fwft.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/img_fifo_fwft_adapter.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_combine_huff_coeff.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_dct8x8_nozigzag.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_dct_aan.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_ff_stuffer.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_huff_top_again.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_hufftab_ac.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_hufftab_dc.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_preamble_mux.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_quantizer.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_rle.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_shift_reg_new.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/jpeg_top.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg/shiftreg_fifo_sc/shiftreg_fifo_sc.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_mipi_dphy/gowin_mipi_dphy.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_pll/gowin_pll.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_pll_24/gowin_pll_24.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_same_wid/gowin_same_wid.v" type="file.verilog" enable="1"/>
        <File path="src/line_combiner.v" type="file.verilog" enable="1"/>
        <File path="src/line_combiner_fifo/line_combiner_fifo.v" type="file.verilog" enable="1"/>
        <File path="src/mipi_csi2_rx/csi2_rx.v" type="file.verilog" enable="1"/>
        <File path="src/mipi_pixel_pll/mipi_pixel_pll.v" type="file.verilog" enable="1"/>
        <File path="src/mipi_rx_advance.v" type="file.verilog" enable="1"/>
        <File path="src/mipi_to_usb_top.v" type="file.verilog" enable="1"/>
        <File path="src/ov5647/ov5647_init/I2C_Interface.v" type="file.verilog" enable="1"/>
        <File path="src/ov5647/ov5647_init/OV5647_Controller.v" type="file.verilog" enable="1"/>
        <File path="src/ov5647/ov5647_init/OV5647_Registers.v" type="file.verilog" enable="1"/>
        <File path="src/usb2_0_softphy/usb2_0_softphy.v" type="file.verilog" enable="1"/>
        <File path="src/usb_device_controller/usb_device_controller.v" type="file.verilog" enable="1"/>
        <File path="src/usb_uvc/usb_uvc_mjpeg_descriptor.v" type="file.verilog" enable="1"/>
        <File path="src/video_config.v" type="file.verilog" enable="1"/>
        <File path="src/video_double_buffer.v" type="file.verilog" enable="1"/>
        <File path="src/video_packet_sender_2.v" type="file.verilog" enable="1"/>
        <File path="src/vidgen.v" type="file.verilog" enable="1"/>
        <File path="src/vidgen_vert.v" type="file.verilog" enable="1"/>
        <File path="src/eyetrack_mipi_fpga.cst" type="file.cst" enable="1"/>
        <File path="src/eyetrack_mipi_fpga.sdc" type="file.sdc" enable="1"/>
    </FileList>
</Project>
