# Makefile for cocotb

# defaults
SIM ?= icarus
TOPLEVEL_LANG ?= verilog

VERILOG_SOURCES ?= $(PWD)/../frame.v
# VERILOG_SOURCES += $(PWD)/../uvc_defs.v

VERILOG_INCLUDE_DIRS ?= $(PWD)/../

# use VHDL_SOURCES for VHDL files

# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL = frame

# MODULE is the basename of the Python test file
MODULE = test_frame

# Example of how to add a verilog define
# this is equivalent to `define INSERT_ERROR in the .v file
# COMPILE_ARGS ?= -DINSERT_ERROR 
# and this is how you'd do something like `define NUM_BITS 12
# COMPILE_ARGS ?= -DNUM_BITS=12

# COMPILE_ARGS ?= -DSIM

# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim