<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
    <Version>beta</Version>
    <Device id="GW5A-25A" package="UBGA324" speed="2" partNumber="GW5A-LV25UG324C2/I1"/>
    <FileList>
        <File path="C:/Gowin/Gowin_V1.9.10_x64/IDE/ipcore/USBTwoSoftPHY/data/usb2_0_softphy_top.v" type="verilog"/>
        <File path="C:/Gowin/Gowin_V1.9.10_x64/IDE/ipcore/USBTwoSoftPHY/data/usb2_0_softphy.v" type="verilog"/>
    </FileList>
    <OptionList>
        <Option type="disable_insert_pad" value="1"/>
        <Option type="enable_dsrm" value="0"/>
        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.10_x64/IDE/ipcore/USBTwoSoftPHY/data"/>
        <Option type="include_path" value="C:/Users/david/Documents/fpga/vidgen_gw5a_devkit/src/usb2_0_softphy/temp/USBTwoSoftPHY"/>
        <Option type="output_file" value="usb2_0_softphy.vg"/>
        <Option type="output_template" value="usb2_0_softphy_tmp.v"/>
        <Option type="ram_balance" value="1"/>
        <Option type="ram_rw_check" value="1"/>
        <Option type="vcc" value="0.9"/>
        <Option type="vccx" value="3.3"/>
        <Option type="verilog_language" value="sysv-2017"/>
    </OptionList>
</Project>
