//Copyright (C)2014-2024 Gowin Semiconductor Corporation. //All rights reserved. //File Title: Post-PnR Verilog Simulation Model file //Tool Version: V1.9.10.03 (64-bit) //Created Time: Tue Jan 28 13:57:40 2025 `timescale 100 ps/100 ps module SPI_Flash_Interface_Top( I_pclk, I_presetn, I_paddr, I_penable, I_psel, I_pwdata, I_pwrite, I_spi_clock, I_spi_rstn, O_prdata, O_pready, O_flash_ck, O_flash_cs_n, IO_flash_hold_n, IO_flash_wp_n, IO_flash_do, IO_flash_di ); input I_pclk; input I_presetn; input [31:0] I_paddr; input I_penable; input I_psel; input [31:0] I_pwdata; input I_pwrite; input I_spi_clock; input I_spi_rstn; output [31:0] O_prdata; output O_pready; output O_flash_ck; output O_flash_cs_n; inout IO_flash_hold_n; inout IO_flash_wp_n; inout IO_flash_do; inout IO_flash_di; wire GND; wire IO_flash_di; wire IO_flash_di_d; wire IO_flash_do; wire IO_flash_do_8; wire IO_flash_do_in; wire IO_flash_hold_n; wire IO_flash_wp_n; wire [31:0] I_paddr; wire I_pclk; wire I_penable; wire I_presetn; wire I_psel; wire [31:0] I_pwdata; wire I_pwrite; wire I_spi_clock; wire I_spi_rstn; wire O_flash_ck; wire O_flash_cs_n; wire [31:0] O_prdata; wire O_pready; wire VCC; wire spi_miso_oe; wire \spiflash_inst/reg_rd_a_Z ; wire \spiflash_inst/reg_rd_a_Z_4 ; wire \spiflash_inst/reg_rd_a_Z_6 ; wire \spiflash_inst/reg_rd_a_Z_8 ; wire \spiflash_inst/n11_6 ; wire \spiflash_inst/spi_3line ; wire \spiflash_inst/spi_lsb ; wire \spiflash_inst/reg_req_r ; wire \spiflash_inst/reg_txf_wr_regclk_Z ; wire \spiflash_inst/reg_rxf_rd_regclk_Z ; wire \spiflash_inst/reg_spi_format_wr_4 ; wire \spiflash_inst/n554_12 ; wire \spiflash_inst/reg_reg_ctrl_wr_7 ; wire \spiflash_inst/spi_trans_end_int_r_15 ; wire \spiflash_inst/reg_txf_clr_regclk_Z ; wire \spiflash_inst/spi_reset_regclk_Z ; wire \spiflash_inst/n220_9 ; wire \spiflash_inst/arb_req_sysclk_Z ; wire \spiflash_inst/n74_7 ; wire \spiflash_inst/arb_rxf_clr_Z ; wire \spiflash_inst/rxf_empty ; wire \spiflash_inst/rxf_clr_level_Z ; wire \spiflash_inst/txf_clr_level_Z ; wire \spiflash_inst/n6_6 ; wire \spiflash_inst/reg_txf_full ; wire \spiflash_inst/txf_empty ; wire \spiflash_inst/rxf_full ; wire \spiflash_inst/spi_reset_sysclk_Z ; wire \spiflash_inst/arb_req_sclk ; wire \spiflash_inst/arb_busy_sysclk ; wire \spiflash_inst/a_level_sync2b_syn2_r ; wire \spiflash_inst/a_level_sync2b_syn3_r ; wire \spiflash_inst/spi_reset_sclk ; wire \spiflash_inst/arb_busy_sclk_Z ; wire \spiflash_inst/tx_ready ; wire \spiflash_inst/arb_req_invalid ; wire \spiflash_inst/txf_rd_Z ; wire \spiflash_inst/rxf_wr_Z ; wire \spiflash_inst/n243_21 ; wire \spiflash_inst/n244_24 ; wire \spiflash_inst/n245_21 ; wire \spiflash_inst/arb_trans_end_sclk_Z_3 ; wire \spiflash_inst/arb_trans_end_sclk_Z_4 ; wire \spiflash_inst/n306_4 ; wire \spiflash_inst/spi_rx_hold_Z_5 ; wire \spiflash_inst/n242_23 ; wire \spiflash_inst/n242_24 ; wire \spiflash_inst/ctrl_word_len_0_7 ; wire \spiflash_inst/txf_rd_Z_4 ; wire \spiflash_inst/n244_35 ; wire \spiflash_inst/n242_33 ; wire \spiflash_inst/spi_rx_hold_Z ; wire \spiflash_inst/rx_bit_cnt_r_4_11 ; wire \spiflash_inst/rx_shift_reg_full_r ; wire \spiflash_inst/master_rxdata_wr_lvl_r ; wire \spiflash_inst/spi_txdata_rd_Z ; wire \spiflash_inst/spi_txdata_rd_Z_8 ; wire \spiflash_inst/spi_txdata_rd_Z_9 ; wire \spiflash_inst/spi_ns_2_21 ; wire \spiflash_inst/spi_txdata_rd_Z_15 ; wire [1:0] \spiflash_inst/arb_addr_len ; wire [4:0] \spiflash_inst/spi_data_len ; wire [5:5] \spiflash_inst/reg_spi_format_r ; wire [30:0] \spiflash_inst/arb_trans_ctrl ; wire [7:0] \spiflash_inst/arb_opcode ; wire [31:0] \spiflash_inst/arb_addr ; wire [13:0] \spiflash_inst/reg_spiif_setting ; wire [1:0] \spiflash_inst/spi_mode ; wire [2:1] \spiflash_inst/arb_cs_r ; wire [5:0] \spiflash_inst/reg_txf_entries ; wire [31:0] \spiflash_inst/txf_rd_data ; wire [5:0] \spiflash_inst/rxf_entries ; wire [31:0] \spiflash_inst/rxf_rd_data ; wire [3:0] \spiflash_inst/ctrl_cs_r ; wire [0:0] \spiflash_inst/sngl_txdata ; wire [31:0] \spiflash_inst/rxf_wr_data_Z ; wire [2:0] \spiflash_inst/spi_cs_r ; wire [0:0] \spiflash_inst/spi_rxdata_Z ; wire \spiflash_inst/u_spi_regif/pstate_nx_r ; wire \spiflash_inst/u_spi_regif/n19_5 ; wire \spiflash_inst/u_spi_regif/n19_6 ; wire \spiflash_inst/u_spi_regif/n19_7 ; wire \spiflash_inst/u_spi_regif/pstate_r ; wire \spiflash_inst/u_spi_reg/reg_spi_format_wr ; wire \spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ; wire \spiflash_inst/u_spi_reg/reg_spi_interface_wr ; wire \spiflash_inst/u_spi_reg/reg_req_r_8 ; wire \spiflash_inst/u_spi_reg/spi_trans_end_int_r_8 ; wire \spiflash_inst/u_spi_reg/txf_thres_int_r_8 ; wire \spiflash_inst/u_spi_reg/rxf_thres_int_r_8 ; wire \spiflash_inst/u_spi_reg/n554_9 ; wire \spiflash_inst/u_spi_reg/n560_9 ; wire \spiflash_inst/u_spi_reg/n562_9 ; wire \spiflash_inst/u_spi_reg/n572_11 ; wire \spiflash_inst/u_spi_reg/n574_11 ; wire \spiflash_inst/u_spi_reg/n576_11 ; wire \spiflash_inst/u_spi_reg/n578_11 ; wire \spiflash_inst/u_spi_reg/n580_12 ; wire \spiflash_inst/u_spi_reg/n582_12 ; wire \spiflash_inst/u_spi_reg/n584_11 ; wire \spiflash_inst/u_spi_reg/n594_13 ; wire \spiflash_inst/u_spi_reg/n602_12 ; wire \spiflash_inst/u_spi_reg/n556_11 ; wire \spiflash_inst/u_spi_reg/n564_11 ; wire \spiflash_inst/u_spi_reg/n566_11 ; wire \spiflash_inst/u_spi_reg/n568_12 ; wire \spiflash_inst/u_spi_reg/n570_12 ; wire \spiflash_inst/u_spi_reg/n586_13 ; wire \spiflash_inst/u_spi_reg/n588_14 ; wire \spiflash_inst/u_spi_reg/n590_15 ; wire \spiflash_inst/u_spi_reg/n592_15 ; wire \spiflash_inst/u_spi_reg/n596_15 ; wire \spiflash_inst/u_spi_reg/n598_15 ; wire \spiflash_inst/u_spi_reg/n600_14 ; wire \spiflash_inst/u_spi_reg/n604_15 ; wire \spiflash_inst/u_spi_reg/n606_17 ; wire \spiflash_inst/u_spi_reg/n608_17 ; wire \spiflash_inst/u_spi_reg/n610_17 ; wire \spiflash_inst/u_spi_reg/n612_17 ; wire \spiflash_inst/u_spi_reg/n613_18 ; wire \spiflash_inst/u_spi_reg/n552_10 ; wire \spiflash_inst/u_spi_reg/n558_13 ; wire \spiflash_inst/u_spi_reg/n440_7 ; wire \spiflash_inst/u_spi_reg/n430_7 ; wire \spiflash_inst/u_spi_reg/n418_7 ; wire \spiflash_inst/u_spi_reg/n88_6 ; wire \spiflash_inst/u_spi_reg/n87_6 ; wire \spiflash_inst/u_spi_reg/n220_6 ; wire \spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ; wire \spiflash_inst/u_spi_reg/reg_reg_cmd_wr_4 ; wire \spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ; wire \spiflash_inst/u_spi_reg/reg_int_en_wr_4 ; wire \spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ; wire \spiflash_inst/u_spi_reg/txf_thres_int_r_9 ; wire \spiflash_inst/u_spi_reg/rxf_thres_int_r_9 ; wire \spiflash_inst/u_spi_reg/n554_10 ; wire \spiflash_inst/u_spi_reg/n554_11 ; wire \spiflash_inst/u_spi_reg/n560_10 ; wire \spiflash_inst/u_spi_reg/n562_10 ; wire \spiflash_inst/u_spi_reg/n572_12 ; wire \spiflash_inst/u_spi_reg/n572_13 ; wire \spiflash_inst/u_spi_reg/n574_12 ; wire \spiflash_inst/u_spi_reg/n574_13 ; wire \spiflash_inst/u_spi_reg/n576_12 ; wire \spiflash_inst/u_spi_reg/n576_13 ; wire \spiflash_inst/u_spi_reg/n578_12 ; wire \spiflash_inst/u_spi_reg/n578_13 ; wire \spiflash_inst/u_spi_reg/n580_13 ; wire \spiflash_inst/u_spi_reg/n580_14 ; wire \spiflash_inst/u_spi_reg/n580_15 ; wire \spiflash_inst/u_spi_reg/n582_13 ; wire \spiflash_inst/u_spi_reg/n582_14 ; wire \spiflash_inst/u_spi_reg/n582_15 ; wire \spiflash_inst/u_spi_reg/n584_13 ; wire \spiflash_inst/u_spi_reg/n584_14 ; wire \spiflash_inst/u_spi_reg/n584_15 ; wire \spiflash_inst/u_spi_reg/n594_14 ; wire \spiflash_inst/u_spi_reg/n594_15 ; wire \spiflash_inst/u_spi_reg/n594_16 ; wire \spiflash_inst/u_spi_reg/n602_13 ; wire \spiflash_inst/u_spi_reg/n602_14 ; wire \spiflash_inst/u_spi_reg/n602_15 ; wire \spiflash_inst/u_spi_reg/n556_12 ; wire \spiflash_inst/u_spi_reg/n556_13 ; wire \spiflash_inst/u_spi_reg/n564_12 ; wire \spiflash_inst/u_spi_reg/n566_12 ; wire \spiflash_inst/u_spi_reg/n568_13 ; wire \spiflash_inst/u_spi_reg/n568_14 ; wire \spiflash_inst/u_spi_reg/n570_13 ; wire \spiflash_inst/u_spi_reg/n570_14 ; wire \spiflash_inst/u_spi_reg/n586_14 ; wire \spiflash_inst/u_spi_reg/n586_15 ; wire \spiflash_inst/u_spi_reg/n588_15 ; wire \spiflash_inst/u_spi_reg/n588_16 ; wire \spiflash_inst/u_spi_reg/n588_17 ; wire \spiflash_inst/u_spi_reg/n590_16 ; wire \spiflash_inst/u_spi_reg/n590_17 ; wire \spiflash_inst/u_spi_reg/n592_16 ; wire \spiflash_inst/u_spi_reg/n592_17 ; wire \spiflash_inst/u_spi_reg/n592_18 ; wire \spiflash_inst/u_spi_reg/n596_16 ; wire \spiflash_inst/u_spi_reg/n596_17 ; wire \spiflash_inst/u_spi_reg/n598_16 ; wire \spiflash_inst/u_spi_reg/n598_17 ; wire \spiflash_inst/u_spi_reg/n598_18 ; wire \spiflash_inst/u_spi_reg/n600_15 ; wire \spiflash_inst/u_spi_reg/n600_16 ; wire \spiflash_inst/u_spi_reg/n600_17 ; wire \spiflash_inst/u_spi_reg/n604_16 ; wire \spiflash_inst/u_spi_reg/n604_17 ; wire \spiflash_inst/u_spi_reg/n606_18 ; wire \spiflash_inst/u_spi_reg/n606_19 ; wire \spiflash_inst/u_spi_reg/n606_20 ; wire \spiflash_inst/u_spi_reg/n606_21 ; wire \spiflash_inst/u_spi_reg/n608_18 ; wire \spiflash_inst/u_spi_reg/n608_19 ; wire \spiflash_inst/u_spi_reg/n608_20 ; wire \spiflash_inst/u_spi_reg/n608_21 ; wire \spiflash_inst/u_spi_reg/n610_18 ; wire \spiflash_inst/u_spi_reg/n610_19 ; wire \spiflash_inst/u_spi_reg/n610_20 ; wire \spiflash_inst/u_spi_reg/n610_21 ; wire \spiflash_inst/u_spi_reg/n612_18 ; wire \spiflash_inst/u_spi_reg/n612_19 ; wire \spiflash_inst/u_spi_reg/n612_20 ; wire \spiflash_inst/u_spi_reg/n612_21 ; wire \spiflash_inst/u_spi_reg/n613_19 ; wire \spiflash_inst/u_spi_reg/n613_20 ; wire \spiflash_inst/u_spi_reg/n613_21 ; wire \spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_5 ; wire \spiflash_inst/u_spi_reg/spi_trans_end_int_r_11 ; wire \spiflash_inst/u_spi_reg/rxf_thres_int_r_10 ; wire \spiflash_inst/u_spi_reg/rxf_thres_int_r_12 ; wire \spiflash_inst/u_spi_reg/n572_14 ; wire \spiflash_inst/u_spi_reg/n584_16 ; wire \spiflash_inst/u_spi_reg/n594_17 ; wire \spiflash_inst/u_spi_reg/n602_16 ; wire \spiflash_inst/u_spi_reg/n570_15 ; wire \spiflash_inst/u_spi_reg/n590_18 ; wire \spiflash_inst/u_spi_reg/n590_19 ; wire \spiflash_inst/u_spi_reg/n592_19 ; wire \spiflash_inst/u_spi_reg/n596_18 ; wire \spiflash_inst/u_spi_reg/n596_19 ; wire \spiflash_inst/u_spi_reg/n598_19 ; wire \spiflash_inst/u_spi_reg/n606_22 ; wire \spiflash_inst/u_spi_reg/n608_22 ; wire \spiflash_inst/u_spi_reg/n610_22 ; wire \spiflash_inst/u_spi_reg/n613_22 ; wire \spiflash_inst/u_spi_reg/n613_23 ; wire \spiflash_inst/u_spi_reg/rxf_thres_int_r_13 ; wire \spiflash_inst/u_spi_reg/rxf_thres_int_r_14 ; wire \spiflash_inst/u_spi_reg/rxf_thres_int_r_15 ; wire \spiflash_inst/u_spi_reg/rxf_thres_int_r_16 ; wire \spiflash_inst/u_spi_reg/spi_trans_end_int_r_13 ; wire \spiflash_inst/u_spi_reg/reg_int_en_wr ; wire \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ; wire \spiflash_inst/u_spi_reg/reg_reg_cmd_wr ; wire \spiflash_inst/u_spi_reg/spi_mode_r_1_8 ; wire \spiflash_inst/u_spi_reg/n584_18 ; wire \spiflash_inst/u_spi_reg/rxf_thres_int_r_18 ; wire \spiflash_inst/u_spi_reg/reg_reg_addr_wr ; wire \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ; wire \spiflash_inst/u_spi_reg/spi_rstn_d2_r ; wire \spiflash_inst/u_spi_reg/spi_rstn_d1_r ; wire \spiflash_inst/u_spi_reg/spi_trans_end_int_r ; wire \spiflash_inst/u_spi_reg/txf_thres_int_r ; wire \spiflash_inst/u_spi_reg/rxf_thres_int_r ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_19_SUM ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_21 ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_20_SUM ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_23 ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_21_SUM ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_25 ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_22_SUM ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_27 ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_23_SUM ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_29 ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_24_SUM ; wire \spiflash_inst/u_spi_reg/txf_threshold_trigger_31 ; wire [20:3] \spiflash_inst/u_spi_reg/reg_reg_ctrl_r ; wire [4:2] \spiflash_inst/u_spi_reg/reg_int_en_r ; wire \spiflash_inst/u_spi_arbiter/n75_6 ; wire \spiflash_inst/u_spi_arbiter/n74_6 ; wire \spiflash_inst/u_spi_arbiter/n73_6 ; wire \spiflash_inst/u_spi_arbiter/n101_5 ; wire \spiflash_inst/u_spi_arbiter/n75_7 ; wire \spiflash_inst/u_spi_arbiter/n74_8 ; wire \spiflash_inst/u_spi_arbiter/n73_8 ; wire \spiflash_inst/u_spi_arbiter/n75_9 ; wire \spiflash_inst/u_spi_arbiter/n74_9 ; wire \spiflash_inst/u_spi_arbiter/n73_10 ; wire \spiflash_inst/u_spi_arbiter/n75_12 ; wire \spiflash_inst/u_spi_arbiter/n75_14 ; wire [0:0] \spiflash_inst/u_spi_arbiter/arb_cs_r_0 ; wire \spiflash_inst/u_spi_fifo/n19_4 ; wire \spiflash_inst/u_spi_fifo/n21_4 ; wire \spiflash_inst/u_spi_fifo/n83_4 ; wire \spiflash_inst/u_spi_fifo/n85_4 ; wire \spiflash_inst/u_spi_fifo/txf_clr_level_7 ; wire \spiflash_inst/u_spi_fifo/rxf_clr_level_7 ; wire \spiflash_inst/u_spi_fifo/rxf_empty_d1 ; wire \spiflash_inst/u_spi_fifo/txf_clr_sclk ; wire \spiflash_inst/u_spi_fifo/txf_clr_ack ; wire \spiflash_inst/u_spi_fifo/rxf_clr_sclk ; wire \spiflash_inst/u_spi_fifo/rxf_clr_ack ; wire \spiflash_inst/u_spi_fifo/rxf_empty_tmp ; wire \spiflash_inst/u_spi_fifo/txf_clr_sync/a_signal_sync1 ; wire \spiflash_inst/u_spi_fifo/txf_clr_ack_sync/a_signal_sync1 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n245_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_0_7 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_4_6 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_2_6 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_4 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_4 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_2_4 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_4 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_5 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_6 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_8 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_5 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_4_6 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_0_8 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_3_8 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_0_9 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_0_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_1_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_2_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_3_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_4_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_5_0_COUT ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n184_1_SUM ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n184_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n185_1_SUM ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n185_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n186_1_SUM ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n186_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n187_1_SUM ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n187_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n188_1_SUM ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/n188_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_7 ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w ; wire [5:1] \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next ; wire [5:1] \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub ; wire \spiflash_inst/u_spi_fifo/rxf_clr_sync/a_signal_sync1 ; wire \spiflash_inst/u_spi_fifo/rxf_clr_ack_sync/a_signal_sync1 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n197_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_0_7 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_4 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_5 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_6 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_8 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_4_8 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_3_8 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_10 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_0_9 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rempty_val ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_0_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_1_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_2_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_3_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_4_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_5_0_COUT ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n184_1_SUM ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n184_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n185_1_SUM ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n185_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n186_1_SUM ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n186_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n187_1_SUM ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n187_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n188_1_SUM ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n188_3 ; wire \spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_7 ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext ; wire [5:1] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next ; wire [5:1] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr ; wire [4:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin ; wire [5:0] \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub ; wire \spiflash_inst/u_spi_sync/spi_reset_sysclk_7 ; wire \spiflash_inst/u_spi_sync/spi_reset_ack ; wire \spiflash_inst/u_spi_sync/arb_req_sync/a_signal_sync1 ; wire \spiflash_inst/u_spi_sync/arb_busy_sync/a_signal_sync1 ; wire \spiflash_inst/u_spi_sync/arb_trans_end_sync/n8_10 ; wire \spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_sync2b_syn1_r ; wire \spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_r ; wire \spiflash_inst/u_spi_sync/spi_reset_sync/a_signal_sync1 ; wire \spiflash_inst/u_spi_sync/spi_reset_ack_sync/a_signal_sync1 ; wire \spiflash_inst/u_spi_ctrl/n1018_10 ; wire \spiflash_inst/u_spi_ctrl/n1018_11 ; wire \spiflash_inst/u_spi_ctrl/n1018_12 ; wire \spiflash_inst/u_spi_ctrl/n1018_13 ; wire \spiflash_inst/u_spi_ctrl/n1022_10 ; wire \spiflash_inst/u_spi_ctrl/n1022_11 ; wire \spiflash_inst/u_spi_ctrl/n1022_12 ; wire \spiflash_inst/u_spi_ctrl/n1022_13 ; wire \spiflash_inst/u_spi_ctrl/n1026_10 ; wire \spiflash_inst/u_spi_ctrl/n1026_11 ; wire \spiflash_inst/u_spi_ctrl/n1026_12 ; wire \spiflash_inst/u_spi_ctrl/n1026_13 ; wire \spiflash_inst/u_spi_ctrl/n1030_10 ; wire \spiflash_inst/u_spi_ctrl/n1030_11 ; wire \spiflash_inst/u_spi_ctrl/n1030_12 ; wire \spiflash_inst/u_spi_ctrl/n1030_13 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_68 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_69 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_70 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_71 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_72 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_73 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_74 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_75 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_76 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_77 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_78 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_79 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_80 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_81 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_82 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_83 ; wire \spiflash_inst/u_spi_ctrl/n852_3 ; wire \spiflash_inst/u_spi_ctrl/n853_3 ; wire \spiflash_inst/u_spi_ctrl/n854_3 ; wire \spiflash_inst/u_spi_ctrl/n855_3 ; wire \spiflash_inst/u_spi_ctrl/n856_3 ; wire \spiflash_inst/u_spi_ctrl/n857_3 ; wire \spiflash_inst/u_spi_ctrl/n858_3 ; wire \spiflash_inst/u_spi_ctrl/n859_3 ; wire \spiflash_inst/u_spi_ctrl/n860_3 ; wire \spiflash_inst/u_spi_ctrl/n861_3 ; wire \spiflash_inst/u_spi_ctrl/n862_3 ; wire \spiflash_inst/u_spi_ctrl/n863_3 ; wire \spiflash_inst/u_spi_ctrl/n864_3 ; wire \spiflash_inst/u_spi_ctrl/n865_3 ; wire \spiflash_inst/u_spi_ctrl/n866_3 ; wire \spiflash_inst/u_spi_ctrl/n867_3 ; wire \spiflash_inst/u_spi_ctrl/n868_3 ; wire \spiflash_inst/u_spi_ctrl/n869_3 ; wire \spiflash_inst/u_spi_ctrl/n870_3 ; wire \spiflash_inst/u_spi_ctrl/n871_3 ; wire \spiflash_inst/u_spi_ctrl/n872_3 ; wire \spiflash_inst/u_spi_ctrl/n873_3 ; wire \spiflash_inst/u_spi_ctrl/n874_3 ; wire \spiflash_inst/u_spi_ctrl/n875_3 ; wire \spiflash_inst/u_spi_ctrl/n876_3 ; wire \spiflash_inst/u_spi_ctrl/n877_3 ; wire \spiflash_inst/u_spi_ctrl/n878_3 ; wire \spiflash_inst/u_spi_ctrl/n879_3 ; wire \spiflash_inst/u_spi_ctrl/n880_3 ; wire \spiflash_inst/u_spi_ctrl/n881_3 ; wire \spiflash_inst/u_spi_ctrl/n882_3 ; wire \spiflash_inst/u_spi_ctrl/n883_3 ; wire \spiflash_inst/u_spi_ctrl/n242_22 ; wire \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_8 ; wire \spiflash_inst/u_spi_ctrl/tx_ready_8 ; wire \spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ; wire \spiflash_inst/u_spi_ctrl/n563_6 ; wire \spiflash_inst/u_spi_ctrl/n562_6 ; wire \spiflash_inst/u_spi_ctrl/n560_6 ; wire \spiflash_inst/u_spi_ctrl/n522_7 ; wire \spiflash_inst/u_spi_ctrl/n521_8 ; wire \spiflash_inst/u_spi_ctrl/n455_6 ; wire \spiflash_inst/u_spi_ctrl/n454_6 ; wire \spiflash_inst/u_spi_ctrl/n453_6 ; wire \spiflash_inst/u_spi_ctrl/n452_6 ; wire \spiflash_inst/u_spi_ctrl/n451_6 ; wire \spiflash_inst/u_spi_ctrl/n354_6 ; wire \spiflash_inst/u_spi_ctrl/n352_6 ; wire \spiflash_inst/u_spi_ctrl/n351_6 ; wire \spiflash_inst/u_spi_ctrl/n350_6 ; wire \spiflash_inst/u_spi_ctrl/n349_6 ; wire \spiflash_inst/u_spi_ctrl/n348_6 ; wire \spiflash_inst/u_spi_ctrl/n347_6 ; wire \spiflash_inst/u_spi_ctrl/n296_6 ; wire \spiflash_inst/u_spi_ctrl/n295_6 ; wire \spiflash_inst/u_spi_ctrl/n21_6 ; wire \spiflash_inst/u_spi_ctrl/txf_rd_Z_3 ; wire \spiflash_inst/u_spi_ctrl/n852_5 ; wire \spiflash_inst/u_spi_ctrl/n853_5 ; wire \spiflash_inst/u_spi_ctrl/n853_6 ; wire \spiflash_inst/u_spi_ctrl/n854_5 ; wire \spiflash_inst/u_spi_ctrl/n856_5 ; wire \spiflash_inst/u_spi_ctrl/n859_5 ; wire \spiflash_inst/u_spi_ctrl/n861_5 ; wire \spiflash_inst/u_spi_ctrl/n862_5 ; wire \spiflash_inst/u_spi_ctrl/n864_5 ; wire \spiflash_inst/u_spi_ctrl/n867_5 ; wire \spiflash_inst/u_spi_ctrl/n869_5 ; wire \spiflash_inst/u_spi_ctrl/n870_5 ; wire \spiflash_inst/u_spi_ctrl/n872_5 ; wire \spiflash_inst/u_spi_ctrl/n875_5 ; wire \spiflash_inst/u_spi_ctrl/n876_4 ; wire \spiflash_inst/u_spi_ctrl/n877_5 ; wire \spiflash_inst/u_spi_ctrl/n878_5 ; wire \spiflash_inst/u_spi_ctrl/n879_4 ; wire \spiflash_inst/u_spi_ctrl/n880_5 ; wire \spiflash_inst/u_spi_ctrl/n881_4 ; wire \spiflash_inst/u_spi_ctrl/n882_4 ; wire \spiflash_inst/u_spi_ctrl/n883_5 ; wire \spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_3 ; wire \spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_4 ; wire \spiflash_inst/u_spi_ctrl/n243_22 ; wire \spiflash_inst/u_spi_ctrl/n243_23 ; wire \spiflash_inst/u_spi_ctrl/n243_24 ; wire \spiflash_inst/u_spi_ctrl/n244_25 ; wire \spiflash_inst/u_spi_ctrl/n244_26 ; wire \spiflash_inst/u_spi_ctrl/n244_27 ; wire \spiflash_inst/u_spi_ctrl/n244_28 ; wire \spiflash_inst/u_spi_ctrl/n245_22 ; wire \spiflash_inst/u_spi_ctrl/n245_23 ; wire \spiflash_inst/u_spi_ctrl/n245_24 ; wire \spiflash_inst/u_spi_ctrl/data_cnt_r_8_9 ; wire \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_9 ; wire \spiflash_inst/u_spi_ctrl/tx_ready_9 ; wire \spiflash_inst/u_spi_ctrl/tx_ready_10 ; wire \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_11 ; wire \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_12 ; wire \spiflash_inst/u_spi_ctrl/ctrl_word_len_3_11 ; wire \spiflash_inst/u_spi_ctrl/n1079_6 ; wire \spiflash_inst/u_spi_ctrl/n1078_6 ; wire \spiflash_inst/u_spi_ctrl/n1077_6 ; wire \spiflash_inst/u_spi_ctrl/n1076_6 ; wire \spiflash_inst/u_spi_ctrl/n564_7 ; wire \spiflash_inst/u_spi_ctrl/n561_7 ; wire \spiflash_inst/u_spi_ctrl/n560_7 ; wire \spiflash_inst/u_spi_ctrl/n522_8 ; wire \spiflash_inst/u_spi_ctrl/n522_9 ; wire \spiflash_inst/u_spi_ctrl/n522_10 ; wire \spiflash_inst/u_spi_ctrl/n521_9 ; wire \spiflash_inst/u_spi_ctrl/n452_7 ; wire \spiflash_inst/u_spi_ctrl/n451_7 ; wire \spiflash_inst/u_spi_ctrl/n353_7 ; wire \spiflash_inst/u_spi_ctrl/n349_7 ; wire \spiflash_inst/u_spi_ctrl/n489_7 ; wire \spiflash_inst/u_spi_ctrl/n488_7 ; wire \spiflash_inst/u_spi_ctrl/ctrl_word_len_0_6 ; wire \spiflash_inst/u_spi_ctrl/n877_6 ; wire \spiflash_inst/u_spi_ctrl/n878_6 ; wire \spiflash_inst/u_spi_ctrl/n880_6 ; wire \spiflash_inst/u_spi_ctrl/n883_6 ; wire \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ; wire \spiflash_inst/u_spi_ctrl/n242_25 ; wire \spiflash_inst/u_spi_ctrl/n243_25 ; wire \spiflash_inst/u_spi_ctrl/n243_26 ; wire \spiflash_inst/u_spi_ctrl/n243_27 ; wire \spiflash_inst/u_spi_ctrl/n243_28 ; wire \spiflash_inst/u_spi_ctrl/n243_29 ; wire \spiflash_inst/u_spi_ctrl/n244_29 ; wire \spiflash_inst/u_spi_ctrl/n244_30 ; wire \spiflash_inst/u_spi_ctrl/n244_32 ; wire \spiflash_inst/u_spi_ctrl/n244_34 ; wire \spiflash_inst/u_spi_ctrl/n244_36 ; wire \spiflash_inst/u_spi_ctrl/n245_25 ; wire \spiflash_inst/u_spi_ctrl/n245_26 ; wire \spiflash_inst/u_spi_ctrl/n245_28 ; wire \spiflash_inst/u_spi_ctrl/n245_29 ; wire \spiflash_inst/u_spi_ctrl/data_cnt_r_8_11 ; wire \spiflash_inst/u_spi_ctrl/tx_ready_11 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_11 ; wire \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_13 ; wire \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_14 ; wire \spiflash_inst/u_spi_ctrl/ctrl_word_len_3_12 ; wire \spiflash_inst/u_spi_ctrl/n1079_7 ; wire \spiflash_inst/u_spi_ctrl/n1079_8 ; wire \spiflash_inst/u_spi_ctrl/n242_30 ; wire \spiflash_inst/u_spi_ctrl/n242_31 ; wire \spiflash_inst/u_spi_ctrl/n243_31 ; wire \spiflash_inst/u_spi_ctrl/n243_32 ; wire \spiflash_inst/u_spi_ctrl/n243_33 ; wire \spiflash_inst/u_spi_ctrl/n243_34 ; wire \spiflash_inst/u_spi_ctrl/n243_35 ; wire \spiflash_inst/u_spi_ctrl/n243_36 ; wire \spiflash_inst/u_spi_ctrl/n243_37 ; wire \spiflash_inst/u_spi_ctrl/n243_38 ; wire \spiflash_inst/u_spi_ctrl/n244_37 ; wire \spiflash_inst/u_spi_ctrl/n244_38 ; wire \spiflash_inst/u_spi_ctrl/n244_39 ; wire \spiflash_inst/u_spi_ctrl/n244_40 ; wire \spiflash_inst/u_spi_ctrl/n244_42 ; wire \spiflash_inst/u_spi_ctrl/n244_43 ; wire \spiflash_inst/u_spi_ctrl/n244_44 ; wire \spiflash_inst/u_spi_ctrl/n244_45 ; wire \spiflash_inst/u_spi_ctrl/n245_30 ; wire \spiflash_inst/u_spi_ctrl/n245_31 ; wire \spiflash_inst/u_spi_ctrl/n245_32 ; wire \spiflash_inst/u_spi_ctrl/n245_33 ; wire \spiflash_inst/u_spi_ctrl/n245_34 ; wire \spiflash_inst/u_spi_ctrl/tx_ready_12 ; wire \spiflash_inst/u_spi_ctrl/tx_ready_13 ; wire \spiflash_inst/u_spi_ctrl/tx_ready_14 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_12 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_13 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_14 ; wire \spiflash_inst/u_spi_ctrl/n243_40 ; wire \spiflash_inst/u_spi_ctrl/n243_41 ; wire \spiflash_inst/u_spi_ctrl/n243_42 ; wire \spiflash_inst/u_spi_ctrl/n244_46 ; wire \spiflash_inst/u_spi_ctrl/n244_47 ; wire \spiflash_inst/u_spi_ctrl/n244_49 ; wire \spiflash_inst/u_spi_ctrl/n244_50 ; wire \spiflash_inst/u_spi_ctrl/n244_52 ; wire \spiflash_inst/u_spi_ctrl/n245_35 ; wire \spiflash_inst/u_spi_ctrl/n245_37 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_15 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_16 ; wire \spiflash_inst/u_spi_ctrl/n244_53 ; wire \spiflash_inst/u_spi_ctrl/n244_54 ; wire \spiflash_inst/u_spi_ctrl/n245_38 ; wire \spiflash_inst/u_spi_ctrl/n244_55 ; wire \spiflash_inst/u_spi_ctrl/n852_9 ; wire \spiflash_inst/u_spi_ctrl/arb_req_invalid_10 ; wire \spiflash_inst/u_spi_ctrl/n243_44 ; wire \spiflash_inst/u_spi_ctrl/n242_36 ; wire \spiflash_inst/u_spi_ctrl/n244_57 ; wire \spiflash_inst/u_spi_ctrl/n348_9 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_18 ; wire \spiflash_inst/u_spi_ctrl/n244_59 ; wire \spiflash_inst/u_spi_ctrl/n242_38 ; wire \spiflash_inst/u_spi_ctrl/n306_6 ; wire \spiflash_inst/u_spi_ctrl/n351_9 ; wire \spiflash_inst/u_spi_ctrl/n353_9 ; wire \spiflash_inst/u_spi_ctrl/n455_9 ; wire \spiflash_inst/u_spi_ctrl/n294_8 ; wire \spiflash_inst/u_spi_ctrl/n244_61 ; wire \spiflash_inst/u_spi_ctrl/n488_9 ; wire \spiflash_inst/u_spi_ctrl/n489_9 ; wire \spiflash_inst/u_spi_ctrl/n702_10 ; wire \spiflash_inst/u_spi_ctrl/n242_42 ; wire \spiflash_inst/u_spi_ctrl/n245_40 ; wire \spiflash_inst/u_spi_ctrl/n242_44 ; wire \spiflash_inst/u_spi_ctrl/n244_63 ; wire \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_11 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ; wire \spiflash_inst/u_spi_ctrl/n521_12 ; wire \spiflash_inst/u_spi_ctrl/n522_13 ; wire \spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ; wire \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_11 ; wire \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_13 ; wire \spiflash_inst/u_spi_ctrl/n245_42 ; wire \spiflash_inst/u_spi_ctrl/n243_46 ; wire \spiflash_inst/u_spi_ctrl/n242_46 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ; wire \spiflash_inst/u_spi_ctrl/n297_8 ; wire \spiflash_inst/u_spi_ctrl/n883_8 ; wire \spiflash_inst/u_spi_ctrl/n882_7 ; wire \spiflash_inst/u_spi_ctrl/n881_7 ; wire \spiflash_inst/u_spi_ctrl/n880_8 ; wire \spiflash_inst/u_spi_ctrl/n879_7 ; wire \spiflash_inst/u_spi_ctrl/n878_8 ; wire \spiflash_inst/u_spi_ctrl/n877_8 ; wire \spiflash_inst/u_spi_ctrl/n876_8 ; wire \spiflash_inst/u_spi_ctrl/n875_7 ; wire \spiflash_inst/u_spi_ctrl/n874_6 ; wire \spiflash_inst/u_spi_ctrl/n873_6 ; wire \spiflash_inst/u_spi_ctrl/n872_7 ; wire \spiflash_inst/u_spi_ctrl/n871_6 ; wire \spiflash_inst/u_spi_ctrl/n870_7 ; wire \spiflash_inst/u_spi_ctrl/n869_7 ; wire \spiflash_inst/u_spi_ctrl/n868_6 ; wire \spiflash_inst/u_spi_ctrl/n867_7 ; wire \spiflash_inst/u_spi_ctrl/n866_6 ; wire \spiflash_inst/u_spi_ctrl/n865_6 ; wire \spiflash_inst/u_spi_ctrl/n864_7 ; wire \spiflash_inst/u_spi_ctrl/n863_6 ; wire \spiflash_inst/u_spi_ctrl/n862_7 ; wire \spiflash_inst/u_spi_ctrl/n861_7 ; wire \spiflash_inst/u_spi_ctrl/n860_6 ; wire \spiflash_inst/u_spi_ctrl/n859_7 ; wire \spiflash_inst/u_spi_ctrl/n858_6 ; wire \spiflash_inst/u_spi_ctrl/n857_6 ; wire \spiflash_inst/u_spi_ctrl/n856_7 ; wire \spiflash_inst/u_spi_ctrl/n855_6 ; wire \spiflash_inst/u_spi_ctrl/n854_7 ; wire \spiflash_inst/u_spi_ctrl/n853_8 ; wire \spiflash_inst/u_spi_ctrl/n852_11 ; wire \spiflash_inst/u_spi_ctrl/n355_9 ; wire \spiflash_inst/u_spi_ctrl/data_cnt_r_8_15 ; wire \spiflash_inst/u_spi_ctrl/n1274_11 ; wire \spiflash_inst/u_spi_ctrl/n244_65 ; wire \spiflash_inst/u_spi_ctrl/n242_48 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_26 ; wire \spiflash_inst/u_spi_ctrl/n561_9 ; wire \spiflash_inst/u_spi_ctrl/n564_9 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_11_13 ; wire \spiflash_inst/u_spi_ctrl/n1068_7 ; wire \spiflash_inst/u_spi_ctrl/n1069_7 ; wire \spiflash_inst/u_spi_ctrl/n1070_7 ; wire \spiflash_inst/u_spi_ctrl/n1071_7 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_16 ; wire \spiflash_inst/u_spi_ctrl/n1064_7 ; wire \spiflash_inst/u_spi_ctrl/n1065_7 ; wire \spiflash_inst/u_spi_ctrl/n1066_7 ; wire \spiflash_inst/u_spi_ctrl/n1067_7 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_16 ; wire \spiflash_inst/u_spi_ctrl/n1060_7 ; wire \spiflash_inst/u_spi_ctrl/n1061_7 ; wire \spiflash_inst/u_spi_ctrl/n1062_7 ; wire \spiflash_inst/u_spi_ctrl/n1063_7 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_16 ; wire \spiflash_inst/u_spi_ctrl/n1056_7 ; wire \spiflash_inst/u_spi_ctrl/n1057_7 ; wire \spiflash_inst/u_spi_ctrl/n1058_7 ; wire \spiflash_inst/u_spi_ctrl/n1059_7 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_16 ; wire \spiflash_inst/u_spi_ctrl/n1052_7 ; wire \spiflash_inst/u_spi_ctrl/n1053_7 ; wire \spiflash_inst/u_spi_ctrl/n1054_7 ; wire \spiflash_inst/u_spi_ctrl/n1055_7 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_19 ; wire \spiflash_inst/u_spi_ctrl/n1048_7 ; wire \spiflash_inst/u_spi_ctrl/n1049_7 ; wire \spiflash_inst/u_spi_ctrl/n1050_7 ; wire \spiflash_inst/u_spi_ctrl/n1051_7 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_13 ; wire \spiflash_inst/u_spi_ctrl/n1076_8 ; wire \spiflash_inst/u_spi_ctrl/n1077_8 ; wire \spiflash_inst/u_spi_ctrl/n1078_8 ; wire \spiflash_inst/u_spi_ctrl/n1079_10 ; wire \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_7_13 ; wire \spiflash_inst/u_spi_ctrl/n1072_7 ; wire \spiflash_inst/u_spi_ctrl/n1073_7 ; wire \spiflash_inst/u_spi_ctrl/n1074_7 ; wire \spiflash_inst/u_spi_ctrl/n1075_7 ; wire \spiflash_inst/u_spi_ctrl/n876_10 ; wire \spiflash_inst/u_spi_ctrl/n958_2 ; wire \spiflash_inst/u_spi_ctrl/n958_3 ; wire \spiflash_inst/u_spi_ctrl/n957_2 ; wire \spiflash_inst/u_spi_ctrl/n957_3 ; wire \spiflash_inst/u_spi_ctrl/n956_2 ; wire \spiflash_inst/u_spi_ctrl/n956_3 ; wire \spiflash_inst/u_spi_ctrl/n955_2 ; wire \spiflash_inst/u_spi_ctrl/n955_3 ; wire \spiflash_inst/u_spi_ctrl/n954_2 ; wire \spiflash_inst/u_spi_ctrl/n954_0_COUT ; wire \spiflash_inst/u_spi_ctrl/n1006_2 ; wire \spiflash_inst/u_spi_ctrl/n1006_3 ; wire \spiflash_inst/u_spi_ctrl/n1005_2 ; wire \spiflash_inst/u_spi_ctrl/n1005_3 ; wire \spiflash_inst/u_spi_ctrl/n1004_2 ; wire \spiflash_inst/u_spi_ctrl/n1004_3 ; wire \spiflash_inst/u_spi_ctrl/n1003_2 ; wire \spiflash_inst/u_spi_ctrl/n1003_3 ; wire \spiflash_inst/u_spi_ctrl/n1002_2 ; wire \spiflash_inst/u_spi_ctrl/n1002_0_COUT ; wire \spiflash_inst/u_spi_ctrl/n14_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n14_3 ; wire \spiflash_inst/u_spi_ctrl/n15_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n15_3 ; wire \spiflash_inst/u_spi_ctrl/n16_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n16_3 ; wire \spiflash_inst/u_spi_ctrl/n17_1_SUM ; wire \spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ; wire \spiflash_inst/u_spi_ctrl/n255_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n255_3 ; wire \spiflash_inst/u_spi_ctrl/n256_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n256_3 ; wire \spiflash_inst/u_spi_ctrl/n257_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n257_3 ; wire \spiflash_inst/u_spi_ctrl/n258_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n258_3 ; wire \spiflash_inst/u_spi_ctrl/n259_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n259_3 ; wire \spiflash_inst/u_spi_ctrl/n260_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n260_3 ; wire \spiflash_inst/u_spi_ctrl/n261_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n261_3 ; wire \spiflash_inst/u_spi_ctrl/n262_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n262_3 ; wire \spiflash_inst/u_spi_ctrl/n263_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n263_3 ; wire \spiflash_inst/u_spi_ctrl/n269_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n269_3 ; wire \spiflash_inst/u_spi_ctrl/n270_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n270_3 ; wire \spiflash_inst/u_spi_ctrl/n271_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n271_3 ; wire \spiflash_inst/u_spi_ctrl/n272_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n272_3 ; wire \spiflash_inst/u_spi_ctrl/n273_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n273_3 ; wire \spiflash_inst/u_spi_ctrl/n274_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n274_3 ; wire \spiflash_inst/u_spi_ctrl/n275_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n275_3 ; wire \spiflash_inst/u_spi_ctrl/n276_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n276_3 ; wire \spiflash_inst/u_spi_ctrl/n277_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n277_3 ; wire \spiflash_inst/u_spi_ctrl/n602_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n602_3 ; wire \spiflash_inst/u_spi_ctrl/n599_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n599_3 ; wire \spiflash_inst/u_spi_ctrl/n597_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n597_3 ; wire \spiflash_inst/u_spi_ctrl/n662_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n662_3 ; wire \spiflash_inst/u_spi_ctrl/n659_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n659_3 ; wire \spiflash_inst/u_spi_ctrl/n657_1_SUM ; wire \spiflash_inst/u_spi_ctrl/n657_3 ; wire \spiflash_inst/u_spi_ctrl/n1018_15 ; wire \spiflash_inst/u_spi_ctrl/n1018_17 ; wire \spiflash_inst/u_spi_ctrl/n1022_15 ; wire \spiflash_inst/u_spi_ctrl/n1022_17 ; wire \spiflash_inst/u_spi_ctrl/n1026_15 ; wire \spiflash_inst/u_spi_ctrl/n1026_17 ; wire \spiflash_inst/u_spi_ctrl/n1030_15 ; wire \spiflash_inst/u_spi_ctrl/n1030_17 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_85 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_87 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_89 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_91 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_93 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_95 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_97 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_99 ; wire \spiflash_inst/u_spi_ctrl/n1018_19 ; wire \spiflash_inst/u_spi_ctrl/n1022_19 ; wire \spiflash_inst/u_spi_ctrl/n1026_19 ; wire \spiflash_inst/u_spi_ctrl/n1030_19 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_101 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_103 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_105 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_107 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_109 ; wire \spiflash_inst/u_spi_ctrl/sngl_txdata_0_111 ; wire [4:0] \spiflash_inst/u_spi_ctrl/tx_ptr ; wire [4:2] \spiflash_inst/u_spi_ctrl/rx_ptr ; wire [4:0] \spiflash_inst/u_spi_ctrl/ctrl_word_len ; wire [1:0] \spiflash_inst/u_spi_ctrl/tx_rx_diff_cnt_r ; wire [8:0] \spiflash_inst/u_spi_ctrl/data_cnt_r ; wire [4:0] \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r ; wire [1:0] \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r ; wire [4:0] \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r ; wire [31:0] \spiflash_inst/u_spi_ctrl/tx_mux_r ; wire [31:0] \spiflash_inst/u_spi_ctrl/rx_shift_reg_r ; wire \spiflash_inst/u_spi_spiif/n338_2 ; wire \spiflash_inst/u_spi_spiif/n341_2 ; wire \spiflash_inst/u_spi_spiif/sclk_1t ; wire \spiflash_inst/u_spi_spiif/master_clk_en ; wire \spiflash_inst/u_spi_spiif/period_cnt_r_7_8 ; wire \spiflash_inst/u_spi_spiif/n287_6 ; wire \spiflash_inst/u_spi_spiif/n263_6 ; wire \spiflash_inst/u_spi_spiif/n200_6 ; wire \spiflash_inst/u_spi_spiif/n199_6 ; wire \spiflash_inst/u_spi_spiif/n197_6 ; wire \spiflash_inst/u_spi_spiif/n132_7 ; wire \spiflash_inst/u_spi_spiif/n131_7 ; wire \spiflash_inst/u_spi_spiif/n129_7 ; wire \spiflash_inst/u_spi_spiif/n128_7 ; wire \spiflash_inst/u_spi_spiif/n127_7 ; wire \spiflash_inst/u_spi_spiif/n126_7 ; wire \spiflash_inst/u_spi_spiif/n125_7 ; wire \spiflash_inst/u_spi_spiif/n79_6 ; wire \spiflash_inst/u_spi_spiif/n78_6 ; wire \spiflash_inst/u_spi_spiif/n77_6 ; wire \spiflash_inst/u_spi_spiif/sclk_1t_4 ; wire \spiflash_inst/u_spi_spiif/sclk_1t_5 ; wire \spiflash_inst/u_spi_spiif/master_clk_en_5 ; wire \spiflash_inst/u_spi_spiif/O_flash_ck_d_3 ; wire \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_3 ; wire \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_4 ; wire \spiflash_inst/u_spi_spiif/spi_ns_2_14 ; wire \spiflash_inst/u_spi_spiif/spi_ns_2_16 ; wire \spiflash_inst/u_spi_spiif/spi_ns_1_14 ; wire \spiflash_inst/u_spi_spiif/spi_ns_1_15 ; wire \spiflash_inst/u_spi_spiif/spi_ns_0_16 ; wire \spiflash_inst/u_spi_spiif/spi_ns_0_17 ; wire \spiflash_inst/u_spi_spiif/period_cnt_r_7_9 ; wire \spiflash_inst/u_spi_spiif/clock_cnt_r_3_9 ; wire \spiflash_inst/u_spi_spiif/n287_7 ; wire \spiflash_inst/u_spi_spiif/n200_7 ; wire \spiflash_inst/u_spi_spiif/n198_7 ; wire \spiflash_inst/u_spi_spiif/n130_8 ; wire \spiflash_inst/u_spi_spiif/n126_8 ; wire \spiflash_inst/u_spi_spiif/master_clk_en_6 ; wire \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_5 ; wire \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_6 ; wire \spiflash_inst/u_spi_spiif/spi_ns_2_17 ; wire \spiflash_inst/u_spi_spiif/spi_ns_2_18 ; wire \spiflash_inst/u_spi_spiif/spi_ns_2_20 ; wire \spiflash_inst/u_spi_spiif/spi_ns_1_16 ; wire \spiflash_inst/u_spi_spiif/spi_ns_1_17 ; wire \spiflash_inst/u_spi_spiif/spi_ns_0_18 ; wire \spiflash_inst/u_spi_spiif/spi_ns_0_19 ; wire \spiflash_inst/u_spi_spiif/spi_ns_0_20 ; wire \spiflash_inst/u_spi_spiif/period_cnt_r_7_11 ; wire \spiflash_inst/u_spi_spiif/clock_cnt_r_3_10 ; wire \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_10 ; wire \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_11 ; wire \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_12 ; wire \spiflash_inst/u_spi_spiif/spi_ns_2_22 ; wire \spiflash_inst/u_spi_spiif/spi_ns_2_23 ; wire \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_13 ; wire \spiflash_inst/u_spi_spiif/clock_cnt_r_3_12 ; wire \spiflash_inst/u_spi_spiif/n198_9 ; wire \spiflash_inst/u_spi_spiif/period_cnt_r_7_13 ; wire \spiflash_inst/u_spi_spiif/n128_10 ; wire \spiflash_inst/u_spi_spiif/n130_10 ; wire \spiflash_inst/u_spi_spiif/spi_ns_2_25 ; wire \spiflash_inst/u_spi_spiif/n132_10 ; wire \spiflash_inst/u_spi_spiif/master_rxdata_wr_lvl_r_10 ; wire \spiflash_inst/u_spi_spiif/n263_9 ; wire \spiflash_inst/u_spi_spiif/master_sclk_r_10 ; wire \spiflash_inst/u_spi_spiif/n331_5 ; wire \spiflash_inst/u_spi_spiif/spi_ns_2_27 ; wire \spiflash_inst/u_spi_spiif/n274_9 ; wire \spiflash_inst/u_spi_spiif/master_clk_d_en_r ; wire \spiflash_inst/u_spi_spiif/spi_rx_hold_d_r ; wire \spiflash_inst/u_spi_spiif/master_sclk_r ; wire \spiflash_inst/u_spi_spiif/n149_17_SUM ; wire \spiflash_inst/u_spi_spiif/n149_20 ; wire \spiflash_inst/u_spi_spiif/n149_18_SUM ; wire \spiflash_inst/u_spi_spiif/n149_22 ; wire \spiflash_inst/u_spi_spiif/n149_19_SUM ; wire \spiflash_inst/u_spi_spiif/n149_24 ; wire \spiflash_inst/u_spi_spiif/n149_20_SUM ; wire \spiflash_inst/u_spi_spiif/n149_26 ; wire \spiflash_inst/u_spi_spiif/n149_21_SUM ; wire \spiflash_inst/u_spi_spiif/n149_28 ; wire \spiflash_inst/u_spi_spiif/n149_22_SUM ; wire \spiflash_inst/u_spi_spiif/n149_30 ; wire \spiflash_inst/u_spi_spiif/n149_23_SUM ; wire \spiflash_inst/u_spi_spiif/n149_32 ; wire \spiflash_inst/u_spi_spiif/n215_9_SUM ; wire \spiflash_inst/u_spi_spiif/n215_12 ; wire \spiflash_inst/u_spi_spiif/n215_10_SUM ; wire \spiflash_inst/u_spi_spiif/n215_14 ; wire \spiflash_inst/u_spi_spiif/n215_11_SUM ; wire \spiflash_inst/u_spi_spiif/n215_16 ; wire \spiflash_inst/u_spi_spiif/n215_12_SUM ; wire \spiflash_inst/u_spi_spiif/n215_18 ; wire \spiflash_inst/u_spi_spiif/n251_1_SUM ; wire \spiflash_inst/u_spi_spiif/n251_3 ; wire \spiflash_inst/u_spi_spiif/n252_1_SUM ; wire \spiflash_inst/u_spi_spiif/n252_3 ; wire \spiflash_inst/u_spi_spiif/n253_1_SUM ; wire \spiflash_inst/u_spi_spiif/n254_2 ; wire \spiflash_inst/u_spi_spiif/spi_clock_inv_6 ; wire \spiflash_inst/u_spi_spiif/latch_out ; wire \spiflash_inst/u_spi_spiif/latch_out_0 ; wire [2:0] \spiflash_inst/u_spi_spiif/spi_ns ; wire [1:0] \spiflash_inst/u_spi_spiif/spi_in_r ; wire [1:0] \spiflash_inst/u_spi_spiif/spi_in_d1_r ; wire [7:0] \spiflash_inst/u_spi_spiif/period_cnt_r ; wire [3:0] \spiflash_inst/u_spi_spiif/clock_cnt_r ; wire \spiflash_inst/u_spi_spiif/master_gclk_0/I_spi_clock_d ; VCC VCC_cZ ( .V(VCC) ); GND GND_cZ ( .G(GND) ); GSR GSR ( .GSRI(VCC) ); OBUF IO_flash_hold_n_obuf ( .I(VCC), .O(IO_flash_hold_n) ); OBUF IO_flash_wp_n_obuf ( .I(VCC), .O(IO_flash_wp_n) ); IOBUF IO_flash_do_iobuf ( .I(VCC), .OEN(IO_flash_do_8), .IO(IO_flash_do), .O(IO_flash_do_in) ); OBUF IO_flash_di_obuf ( .I(IO_flash_di_d), .O(IO_flash_di) ); INV IO_flash_do_s5 ( .I(spi_miso_oe), .O(IO_flash_do_8) ); LUT3 \spiflash_inst/u_spi_regif/reg_rd_a_Z_s ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/reg_rd_a_Z_8 ), .I2(\spiflash_inst/reg_rd_a_Z_6 ), .F(\spiflash_inst/reg_rd_a_Z ) ); defparam \spiflash_inst/u_spi_regif/reg_rd_a_Z_s .INIT=8'hD0; LUT3 \spiflash_inst/u_spi_regif/pstate_nx_r_s1 ( .I0(I_psel), .I1(O_pready), .I2(\spiflash_inst/u_spi_regif/pstate_r ), .F(\spiflash_inst/u_spi_regif/pstate_nx_r ) ); defparam \spiflash_inst/u_spi_regif/pstate_nx_r_s1 .INIT=8'h3A; LUT4 \spiflash_inst/u_spi_regif/n19_s1 ( .I0(\spiflash_inst/u_spi_regif/n19_6 ), .I1(\spiflash_inst/u_spi_regif/n19_7 ), .I2(\spiflash_inst/reg_rd_a_Z_4 ), .I3(\spiflash_inst/u_spi_regif/pstate_nx_r ), .F(\spiflash_inst/u_spi_regif/n19_5 ) ); defparam \spiflash_inst/u_spi_regif/n19_s1 .INIT=16'hDFFF; LUT3 \spiflash_inst/u_spi_regif/reg_rd_a_Z_s0 ( .I0(I_paddr[2]), .I1(I_paddr[3]), .I2(\spiflash_inst/n554_12 ), .F(\spiflash_inst/reg_rd_a_Z_4 ) ); defparam \spiflash_inst/u_spi_regif/reg_rd_a_Z_s0 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_regif/reg_rd_a_Z_s2 ( .I0(I_penable), .I1(O_pready), .I2(I_pwrite), .I3(I_psel), .F(\spiflash_inst/reg_rd_a_Z_6 ) ); defparam \spiflash_inst/u_spi_regif/reg_rd_a_Z_s2 .INIT=16'h0700; LUT3 \spiflash_inst/u_spi_regif/n19_s2 ( .I0(\spiflash_inst/reg_rd_a_Z_8 ), .I1(\spiflash_inst/reg_txf_full ), .I2(I_pwrite), .F(\spiflash_inst/u_spi_regif/n19_6 ) ); defparam \spiflash_inst/u_spi_regif/n19_s2 .INIT=8'hC5; LUT4 \spiflash_inst/u_spi_regif/n19_s3 ( .I0(\spiflash_inst/ctrl_word_len_0_7 ), .I1(\spiflash_inst/arb_busy_sysclk ), .I2(\spiflash_inst/reg_req_r ), .I3(\spiflash_inst/n220_9 ), .F(\spiflash_inst/u_spi_regif/n19_7 ) ); defparam \spiflash_inst/u_spi_regif/n19_s3 .INIT=16'h0700; LUT3 \spiflash_inst/u_spi_regif/reg_rd_a_Z_s3 ( .I0(\spiflash_inst/rxf_empty ), .I1(\spiflash_inst/arb_cs_r [1]), .I2(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/reg_rd_a_Z_8 ) ); defparam \spiflash_inst/u_spi_regif/reg_rd_a_Z_s3 .INIT=8'h01; DFFCE \spiflash_inst/u_spi_regif/pstate_r_s0 ( .D(\spiflash_inst/u_spi_regif/pstate_nx_r ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_regif/pstate_r ) ); defparam \spiflash_inst/u_spi_regif/pstate_r_s0 .INIT=1'b0; DFFPE \spiflash_inst/u_spi_regif/pready_r_s0 ( .D(\spiflash_inst/u_spi_regif/n19_5 ), .CLK(I_pclk), .CE(VCC), .PRESET(\spiflash_inst/n11_6 ), .Q(O_pready) ); defparam \spiflash_inst/u_spi_regif/pready_r_s0 .INIT=1'b1; INV \spiflash_inst/u_spi_regif/n11_s2 ( .I(I_presetn), .O(\spiflash_inst/n11_6 ) ); LUT2 \spiflash_inst/u_spi_reg/reg_spi_format_wr_s0 ( .I0(\spiflash_inst/reg_spi_format_wr_4 ), .I1(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .F(\spiflash_inst/u_spi_reg/reg_spi_format_wr ) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_wr_s0 .INIT=4'h8; LUT2 \spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_s0 ( .I0(\spiflash_inst/reg_spi_format_wr_4 ), .I1(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_s0 .INIT=4'h8; LUT2 \spiflash_inst/u_spi_reg/reg_spi_interface_wr_s0 ( .I0(\spiflash_inst/reg_spi_format_wr_4 ), .I1(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ) ); defparam \spiflash_inst/u_spi_reg/reg_spi_interface_wr_s0 .INIT=4'h8; LUT3 \spiflash_inst/u_spi_reg/reg_txf_wr_regclk_Z_s0 ( .I0(\spiflash_inst/reg_txf_full ), .I1(\spiflash_inst/reg_rd_a_Z_4 ), .I2(\spiflash_inst/reg_spi_format_wr_4 ), .F(\spiflash_inst/reg_txf_wr_regclk_Z ) ); defparam \spiflash_inst/u_spi_reg/reg_txf_wr_regclk_Z_s0 .INIT=8'h40; LUT3 \spiflash_inst/u_spi_reg/reg_rxf_rd_regclk_Z_s ( .I0(\spiflash_inst/reg_rd_a_Z_8 ), .I1(\spiflash_inst/reg_rd_a_Z_4 ), .I2(\spiflash_inst/reg_rd_a_Z_6 ), .F(\spiflash_inst/reg_rxf_rd_regclk_Z ) ); defparam \spiflash_inst/u_spi_reg/reg_rxf_rd_regclk_Z_s .INIT=8'h80; LUT2 \spiflash_inst/u_spi_reg/reg_req_r_s3 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr ), .I1(\spiflash_inst/u_spi_reg/n220_6 ), .F(\spiflash_inst/u_spi_reg/reg_req_r_8 ) ); defparam \spiflash_inst/u_spi_reg/reg_req_r_s3 .INIT=4'hB; LUT4 \spiflash_inst/u_spi_reg/spi_trans_end_int_r_s3 ( .I0(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_13 ), .I1(I_pwdata[4]), .I2(\spiflash_inst/spi_trans_end_int_r_15 ), .I3(\spiflash_inst/u_spi_reg/reg_int_en_r [4]), .F(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_8 ) ); defparam \spiflash_inst/u_spi_reg/spi_trans_end_int_r_s3 .INIT=16'hF8FF; LUT4 \spiflash_inst/u_spi_reg/txf_thres_int_r_s3 ( .I0(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_13 ), .I1(I_pwdata[3]), .I2(\spiflash_inst/u_spi_reg/reg_int_en_r [3]), .I3(\spiflash_inst/u_spi_reg/txf_thres_int_r_9 ), .F(\spiflash_inst/u_spi_reg/txf_thres_int_r_8 ) ); defparam \spiflash_inst/u_spi_reg/txf_thres_int_r_s3 .INIT=16'h8FFF; LUT4 \spiflash_inst/u_spi_reg/rxf_thres_int_r_s3 ( .I0(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_13 ), .I1(I_pwdata[2]), .I2(\spiflash_inst/u_spi_reg/rxf_thres_int_r_9 ), .I3(\spiflash_inst/u_spi_reg/reg_int_en_r [2]), .F(\spiflash_inst/u_spi_reg/rxf_thres_int_r_8 ) ); defparam \spiflash_inst/u_spi_reg/rxf_thres_int_r_s3 .INIT=16'hF8FF; LUT4 \spiflash_inst/u_spi_reg/n554_s5 ( .I0(\spiflash_inst/u_spi_reg/n554_10 ), .I1(\spiflash_inst/arb_trans_ctrl [30]), .I2(\spiflash_inst/u_spi_reg/n554_11 ), .I3(\spiflash_inst/n554_12 ), .F(\spiflash_inst/u_spi_reg/n554_9 ) ); defparam \spiflash_inst/u_spi_reg/n554_s5 .INIT=16'hF800; LUT4 \spiflash_inst/u_spi_reg/n560_s5 ( .I0(\spiflash_inst/u_spi_reg/n554_10 ), .I1(\spiflash_inst/arb_trans_ctrl [27]), .I2(\spiflash_inst/u_spi_reg/n560_10 ), .I3(\spiflash_inst/n554_12 ), .F(\spiflash_inst/u_spi_reg/n560_9 ) ); defparam \spiflash_inst/u_spi_reg/n560_s5 .INIT=16'hF800; LUT3 \spiflash_inst/u_spi_reg/n562_s5 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [26]), .I2(\spiflash_inst/u_spi_reg/n562_10 ), .F(\spiflash_inst/u_spi_reg/n562_9 ) ); defparam \spiflash_inst/u_spi_reg/n562_s5 .INIT=8'h8F; LUT4 \spiflash_inst/u_spi_reg/n572_s7 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I1(\spiflash_inst/arb_addr [21]), .I2(\spiflash_inst/u_spi_reg/n572_12 ), .I3(\spiflash_inst/u_spi_reg/n572_13 ), .F(\spiflash_inst/u_spi_reg/n572_11 ) ); defparam \spiflash_inst/u_spi_reg/n572_s7 .INIT=16'h8FFF; LUT4 \spiflash_inst/u_spi_reg/n574_s7 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I1(\spiflash_inst/arb_addr [20]), .I2(\spiflash_inst/u_spi_reg/n574_12 ), .I3(\spiflash_inst/u_spi_reg/n574_13 ), .F(\spiflash_inst/u_spi_reg/n574_11 ) ); defparam \spiflash_inst/u_spi_reg/n574_s7 .INIT=16'h8FFF; LUT4 \spiflash_inst/u_spi_reg/n576_s7 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I1(\spiflash_inst/arb_addr [19]), .I2(\spiflash_inst/u_spi_reg/n576_12 ), .I3(\spiflash_inst/u_spi_reg/n576_13 ), .F(\spiflash_inst/u_spi_reg/n576_11 ) ); defparam \spiflash_inst/u_spi_reg/n576_s7 .INIT=16'h8FFF; LUT4 \spiflash_inst/u_spi_reg/n578_s7 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I1(\spiflash_inst/arb_addr [18]), .I2(\spiflash_inst/u_spi_reg/n578_12 ), .I3(\spiflash_inst/u_spi_reg/n578_13 ), .F(\spiflash_inst/u_spi_reg/n578_11 ) ); defparam \spiflash_inst/u_spi_reg/n578_s7 .INIT=16'h8FFF; LUT3 \spiflash_inst/u_spi_reg/n580_s8 ( .I0(\spiflash_inst/u_spi_reg/n580_13 ), .I1(\spiflash_inst/u_spi_reg/n580_14 ), .I2(\spiflash_inst/u_spi_reg/n580_15 ), .F(\spiflash_inst/u_spi_reg/n580_12 ) ); defparam \spiflash_inst/u_spi_reg/n580_s8 .INIT=8'h7F; LUT3 \spiflash_inst/u_spi_reg/n582_s8 ( .I0(\spiflash_inst/u_spi_reg/n582_13 ), .I1(\spiflash_inst/u_spi_reg/n582_14 ), .I2(\spiflash_inst/u_spi_reg/n582_15 ), .F(\spiflash_inst/u_spi_reg/n582_12 ) ); defparam \spiflash_inst/u_spi_reg/n582_s8 .INIT=8'h7F; LUT4 \spiflash_inst/u_spi_reg/n584_s7 ( .I0(\spiflash_inst/u_spi_reg/n584_18 ), .I1(\spiflash_inst/u_spi_reg/n584_13 ), .I2(\spiflash_inst/u_spi_reg/n584_14 ), .I3(\spiflash_inst/u_spi_reg/n584_15 ), .F(\spiflash_inst/u_spi_reg/n584_11 ) ); defparam \spiflash_inst/u_spi_reg/n584_s7 .INIT=16'h8FFF; LUT3 \spiflash_inst/u_spi_reg/n594_s9 ( .I0(\spiflash_inst/u_spi_reg/n594_14 ), .I1(\spiflash_inst/u_spi_reg/n594_15 ), .I2(\spiflash_inst/u_spi_reg/n594_16 ), .F(\spiflash_inst/u_spi_reg/n594_13 ) ); defparam \spiflash_inst/u_spi_reg/n594_s9 .INIT=8'h7F; LUT3 \spiflash_inst/u_spi_reg/n602_s8 ( .I0(\spiflash_inst/u_spi_reg/n602_13 ), .I1(\spiflash_inst/u_spi_reg/n602_14 ), .I2(\spiflash_inst/u_spi_reg/n602_15 ), .F(\spiflash_inst/u_spi_reg/n602_12 ) ); defparam \spiflash_inst/u_spi_reg/n602_s8 .INIT=8'h7F; LUT4 \spiflash_inst/u_spi_reg/n556_s7 ( .I0(\spiflash_inst/u_spi_reg/n556_12 ), .I1(\spiflash_inst/u_spi_reg/n556_13 ), .I2(I_paddr[2]), .I3(\spiflash_inst/n554_12 ), .F(\spiflash_inst/u_spi_reg/n556_11 ) ); defparam \spiflash_inst/u_spi_reg/n556_s7 .INIT=16'hCA00; LUT3 \spiflash_inst/u_spi_reg/n564_s7 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [25]), .I2(\spiflash_inst/u_spi_reg/n564_12 ), .F(\spiflash_inst/u_spi_reg/n564_11 ) ); defparam \spiflash_inst/u_spi_reg/n564_s7 .INIT=8'h8F; LUT3 \spiflash_inst/u_spi_reg/n566_s7 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [24]), .I2(\spiflash_inst/u_spi_reg/n566_12 ), .F(\spiflash_inst/u_spi_reg/n566_11 ) ); defparam \spiflash_inst/u_spi_reg/n566_s7 .INIT=8'h8F; LUT2 \spiflash_inst/u_spi_reg/n568_s8 ( .I0(\spiflash_inst/u_spi_reg/n568_13 ), .I1(\spiflash_inst/u_spi_reg/n568_14 ), .F(\spiflash_inst/u_spi_reg/n568_12 ) ); defparam \spiflash_inst/u_spi_reg/n568_s8 .INIT=4'h7; LUT4 \spiflash_inst/u_spi_reg/n570_s8 ( .I0(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I1(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [19]), .I2(\spiflash_inst/u_spi_reg/n570_13 ), .I3(\spiflash_inst/u_spi_reg/n570_14 ), .F(\spiflash_inst/u_spi_reg/n570_12 ) ); defparam \spiflash_inst/u_spi_reg/n570_s8 .INIT=16'hF8FF; LUT4 \spiflash_inst/u_spi_reg/n586_s9 ( .I0(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I1(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [11]), .I2(\spiflash_inst/u_spi_reg/n586_14 ), .I3(\spiflash_inst/u_spi_reg/n586_15 ), .F(\spiflash_inst/u_spi_reg/n586_13 ) ); defparam \spiflash_inst/u_spi_reg/n586_s9 .INIT=16'h8FFF; LUT3 \spiflash_inst/u_spi_reg/n588_s10 ( .I0(\spiflash_inst/u_spi_reg/n588_15 ), .I1(\spiflash_inst/u_spi_reg/n588_16 ), .I2(\spiflash_inst/u_spi_reg/n588_17 ), .F(\spiflash_inst/u_spi_reg/n588_14 ) ); defparam \spiflash_inst/u_spi_reg/n588_s10 .INIT=8'h7F; LUT4 \spiflash_inst/u_spi_reg/n590_s11 ( .I0(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I1(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [9]), .I2(\spiflash_inst/u_spi_reg/n590_16 ), .I3(\spiflash_inst/u_spi_reg/n590_17 ), .F(\spiflash_inst/u_spi_reg/n590_15 ) ); defparam \spiflash_inst/u_spi_reg/n590_s11 .INIT=16'h8FFF; LUT3 \spiflash_inst/u_spi_reg/n592_s11 ( .I0(\spiflash_inst/u_spi_reg/n592_16 ), .I1(\spiflash_inst/u_spi_reg/n592_17 ), .I2(\spiflash_inst/u_spi_reg/n592_18 ), .F(\spiflash_inst/u_spi_reg/n592_15 ) ); defparam \spiflash_inst/u_spi_reg/n592_s11 .INIT=8'h7F; LUT2 \spiflash_inst/u_spi_reg/n596_s11 ( .I0(\spiflash_inst/u_spi_reg/n596_16 ), .I1(\spiflash_inst/u_spi_reg/n596_17 ), .F(\spiflash_inst/u_spi_reg/n596_15 ) ); defparam \spiflash_inst/u_spi_reg/n596_s11 .INIT=4'h7; LUT3 \spiflash_inst/u_spi_reg/n598_s11 ( .I0(\spiflash_inst/u_spi_reg/n598_16 ), .I1(\spiflash_inst/u_spi_reg/n598_17 ), .I2(\spiflash_inst/u_spi_reg/n598_18 ), .F(\spiflash_inst/u_spi_reg/n598_15 ) ); defparam \spiflash_inst/u_spi_reg/n598_s11 .INIT=8'h7F; LUT3 \spiflash_inst/u_spi_reg/n600_s10 ( .I0(\spiflash_inst/u_spi_reg/n600_15 ), .I1(\spiflash_inst/u_spi_reg/n600_16 ), .I2(\spiflash_inst/u_spi_reg/n600_17 ), .F(\spiflash_inst/u_spi_reg/n600_14 ) ); defparam \spiflash_inst/u_spi_reg/n600_s10 .INIT=8'h7F; LUT4 \spiflash_inst/u_spi_reg/n604_s11 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [5]), .I2(\spiflash_inst/u_spi_reg/n604_16 ), .I3(\spiflash_inst/u_spi_reg/n604_17 ), .F(\spiflash_inst/u_spi_reg/n604_15 ) ); defparam \spiflash_inst/u_spi_reg/n604_s11 .INIT=16'h8FFF; LUT4 \spiflash_inst/u_spi_reg/n606_s13 ( .I0(\spiflash_inst/u_spi_reg/n606_18 ), .I1(\spiflash_inst/u_spi_reg/n606_19 ), .I2(\spiflash_inst/u_spi_reg/n606_20 ), .I3(\spiflash_inst/u_spi_reg/n606_21 ), .F(\spiflash_inst/u_spi_reg/n606_17 ) ); defparam \spiflash_inst/u_spi_reg/n606_s13 .INIT=16'h7FFF; LUT4 \spiflash_inst/u_spi_reg/n608_s13 ( .I0(\spiflash_inst/u_spi_reg/n608_18 ), .I1(\spiflash_inst/u_spi_reg/n608_19 ), .I2(\spiflash_inst/u_spi_reg/n608_20 ), .I3(\spiflash_inst/u_spi_reg/n608_21 ), .F(\spiflash_inst/u_spi_reg/n608_17 ) ); defparam \spiflash_inst/u_spi_reg/n608_s13 .INIT=16'h7FFF; LUT4 \spiflash_inst/u_spi_reg/n610_s13 ( .I0(\spiflash_inst/u_spi_reg/n610_18 ), .I1(\spiflash_inst/u_spi_reg/n610_19 ), .I2(\spiflash_inst/u_spi_reg/n610_20 ), .I3(\spiflash_inst/u_spi_reg/n610_21 ), .F(\spiflash_inst/u_spi_reg/n610_17 ) ); defparam \spiflash_inst/u_spi_reg/n610_s13 .INIT=16'h7FFF; LUT4 \spiflash_inst/u_spi_reg/n612_s13 ( .I0(\spiflash_inst/u_spi_reg/n612_18 ), .I1(\spiflash_inst/u_spi_reg/n612_19 ), .I2(\spiflash_inst/u_spi_reg/n612_20 ), .I3(\spiflash_inst/u_spi_reg/n612_21 ), .F(\spiflash_inst/u_spi_reg/n612_17 ) ); defparam \spiflash_inst/u_spi_reg/n612_s13 .INIT=16'hBFFF; LUT3 \spiflash_inst/u_spi_reg/n613_s14 ( .I0(\spiflash_inst/u_spi_reg/n613_19 ), .I1(\spiflash_inst/u_spi_reg/n613_20 ), .I2(\spiflash_inst/u_spi_reg/n613_21 ), .F(\spiflash_inst/u_spi_reg/n613_18 ) ); defparam \spiflash_inst/u_spi_reg/n613_s14 .INIT=8'hBF; LUT4 \spiflash_inst/u_spi_reg/n552_s5 ( .I0(\spiflash_inst/arb_addr [31]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/rxf_rd_data [31]), .I3(\spiflash_inst/reg_rd_a_Z_4 ), .F(\spiflash_inst/u_spi_reg/n552_10 ) ); defparam \spiflash_inst/u_spi_reg/n552_s5 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_reg/n558_s8 ( .I0(\spiflash_inst/arb_addr [28]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/rxf_rd_data [28]), .I3(\spiflash_inst/reg_rd_a_Z_4 ), .F(\spiflash_inst/u_spi_reg/n558_13 ) ); defparam \spiflash_inst/u_spi_reg/n558_s8 .INIT=16'hF888; LUT3 \spiflash_inst/u_spi_reg/n440_s3 ( .I0(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_13 ), .I1(I_pwdata[2]), .I2(\spiflash_inst/u_spi_reg/rxf_thres_int_r_9 ), .F(\spiflash_inst/u_spi_reg/n440_7 ) ); defparam \spiflash_inst/u_spi_reg/n440_s3 .INIT=8'h70; LUT4 \spiflash_inst/u_spi_reg/n430_s3 ( .I0(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_13 ), .I1(I_pwdata[3]), .I2(\spiflash_inst/u_spi_reg/txf_thres_int_r_9 ), .I3(\spiflash_inst/u_spi_reg/reg_int_en_r [3]), .F(\spiflash_inst/u_spi_reg/n430_7 ) ); defparam \spiflash_inst/u_spi_reg/n430_s3 .INIT=16'h0700; LUT4 \spiflash_inst/u_spi_reg/n418_s3 ( .I0(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_13 ), .I1(I_pwdata[4]), .I2(\spiflash_inst/spi_trans_end_int_r_15 ), .I3(\spiflash_inst/u_spi_reg/reg_int_en_r [4]), .F(\spiflash_inst/u_spi_reg/n418_7 ) ); defparam \spiflash_inst/u_spi_reg/n418_s3 .INIT=16'h7000; LUT2 \spiflash_inst/u_spi_reg/n88_s2 ( .I0(\spiflash_inst/u_spi_reg/spi_rstn_d2_r ), .I1(I_pwdata[0]), .F(\spiflash_inst/u_spi_reg/n88_6 ) ); defparam \spiflash_inst/u_spi_reg/n88_s2 .INIT=4'h4; LUT2 \spiflash_inst/u_spi_reg/n87_s2 ( .I0(\spiflash_inst/u_spi_reg/spi_rstn_d2_r ), .I1(I_pwdata[1]), .F(\spiflash_inst/u_spi_reg/n87_6 ) ); defparam \spiflash_inst/u_spi_reg/n87_s2 .INIT=4'h4; LUT3 \spiflash_inst/u_spi_reg/n220_s2 ( .I0(\spiflash_inst/spi_trans_end_int_r_15 ), .I1(\spiflash_inst/n220_9 ), .I2(\spiflash_inst/spi_reset_regclk_Z ), .F(\spiflash_inst/u_spi_reg/n220_6 ) ); defparam \spiflash_inst/u_spi_reg/n220_s2 .INIT=8'h07; LUT4 \spiflash_inst/u_spi_reg/reg_spi_format_wr_s1 ( .I0(I_pwrite), .I1(I_psel), .I2(O_pready), .I3(I_penable), .F(\spiflash_inst/reg_spi_format_wr_4 ) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_wr_s1 .INIT=16'h8000; LUT4 \spiflash_inst/u_spi_reg/reg_spi_format_wr_s2 ( .I0(I_paddr[5]), .I1(I_paddr[6]), .I2(I_paddr[4]), .I3(\spiflash_inst/u_spi_reg/n554_10 ), .F(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_wr_s2 .INIT=16'h1000; LUT3 \spiflash_inst/u_spi_reg/reg_reg_cmd_wr_s1 ( .I0(I_paddr[3]), .I1(I_paddr[2]), .I2(\spiflash_inst/n554_12 ), .F(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr_4 ) ); defparam \spiflash_inst/u_spi_reg/reg_reg_cmd_wr_s1 .INIT=8'h40; LUT3 \spiflash_inst/u_spi_reg/reg_reg_addr_wr_s1 ( .I0(I_paddr[2]), .I1(I_paddr[3]), .I2(\spiflash_inst/n554_12 ), .F(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_wr_s1 .INIT=8'h40; LUT3 \spiflash_inst/u_spi_reg/reg_int_en_wr_s1 ( .I0(I_paddr[2]), .I1(I_paddr[3]), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_5 ), .F(\spiflash_inst/u_spi_reg/reg_int_en_wr_4 ) ); defparam \spiflash_inst/u_spi_reg/reg_int_en_wr_s1 .INIT=8'h40; LUT4 \spiflash_inst/u_spi_reg/reg_spi_interface_wr_s1 ( .I0(I_paddr[4]), .I1(I_paddr[5]), .I2(I_paddr[6]), .I3(\spiflash_inst/u_spi_reg/n554_10 ), .F(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ) ); defparam \spiflash_inst/u_spi_reg/reg_spi_interface_wr_s1 .INIT=16'h1000; LUT3 \spiflash_inst/u_spi_reg/txf_thres_int_r_s4 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [20]), .I1(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [19]), .I2(\spiflash_inst/u_spi_reg/txf_threshold_trigger_31 ), .F(\spiflash_inst/u_spi_reg/txf_thres_int_r_9 ) ); defparam \spiflash_inst/u_spi_reg/txf_thres_int_r_s4 .INIT=8'h01; LUT4 \spiflash_inst/u_spi_reg/rxf_thres_int_r_s4 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [10]), .I1(\spiflash_inst/u_spi_reg/rxf_thres_int_r_10 ), .I2(\spiflash_inst/u_spi_reg/rxf_thres_int_r_18 ), .I3(\spiflash_inst/u_spi_reg/rxf_thres_int_r_12 ), .F(\spiflash_inst/u_spi_reg/rxf_thres_int_r_9 ) ); defparam \spiflash_inst/u_spi_reg/rxf_thres_int_r_s4 .INIT=16'h7100; LUT2 \spiflash_inst/u_spi_reg/n554_s6 ( .I0(I_paddr[2]), .I1(I_paddr[3]), .F(\spiflash_inst/u_spi_reg/n554_10 ) ); defparam \spiflash_inst/u_spi_reg/n554_s6 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_reg/n554_s7 ( .I0(\spiflash_inst/arb_addr [30]), .I1(\spiflash_inst/rxf_rd_data [30]), .I2(I_paddr[2]), .I3(I_paddr[3]), .F(\spiflash_inst/u_spi_reg/n554_11 ) ); defparam \spiflash_inst/u_spi_reg/n554_s7 .INIT=16'hCA00; LUT3 \spiflash_inst/u_spi_reg/n554_s8 ( .I0(I_paddr[4]), .I1(I_paddr[6]), .I2(I_paddr[5]), .F(\spiflash_inst/n554_12 ) ); defparam \spiflash_inst/u_spi_reg/n554_s8 .INIT=8'h10; LUT4 \spiflash_inst/u_spi_reg/n560_s6 ( .I0(\spiflash_inst/arb_addr [27]), .I1(\spiflash_inst/rxf_rd_data [27]), .I2(I_paddr[2]), .I3(I_paddr[3]), .F(\spiflash_inst/u_spi_reg/n560_10 ) ); defparam \spiflash_inst/u_spi_reg/n560_s6 .INIT=16'hCA00; LUT4 \spiflash_inst/u_spi_reg/n562_s6 ( .I0(\spiflash_inst/arb_addr [26]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/rxf_rd_data [26]), .I3(\spiflash_inst/reg_rd_a_Z_4 ), .F(\spiflash_inst/u_spi_reg/n562_10 ) ); defparam \spiflash_inst/u_spi_reg/n562_s6 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n572_s8 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [21]), .I2(\spiflash_inst/reg_txf_entries [5]), .I3(\spiflash_inst/u_spi_reg/n572_14 ), .F(\spiflash_inst/u_spi_reg/n572_12 ) ); defparam \spiflash_inst/u_spi_reg/n572_s8 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n572_s9 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [18]), .I1(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I2(\spiflash_inst/arb_trans_ctrl [21]), .I3(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .F(\spiflash_inst/u_spi_reg/n572_13 ) ); defparam \spiflash_inst/u_spi_reg/n572_s9 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n574_s8 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [20]), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [17]), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/n574_12 ) ); defparam \spiflash_inst/u_spi_reg/n574_s8 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n574_s9 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [20]), .I2(\spiflash_inst/reg_txf_entries [4]), .I3(\spiflash_inst/u_spi_reg/n572_14 ), .F(\spiflash_inst/u_spi_reg/n574_13 ) ); defparam \spiflash_inst/u_spi_reg/n574_s9 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n576_s8 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [19]), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [16]), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/n576_12 ) ); defparam \spiflash_inst/u_spi_reg/n576_s8 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n576_s9 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [19]), .I2(\spiflash_inst/reg_txf_entries [3]), .I3(\spiflash_inst/u_spi_reg/n572_14 ), .F(\spiflash_inst/u_spi_reg/n576_13 ) ); defparam \spiflash_inst/u_spi_reg/n576_s9 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n578_s8 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [18]), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [15]), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/n578_12 ) ); defparam \spiflash_inst/u_spi_reg/n578_s8 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n578_s9 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [18]), .I2(\spiflash_inst/reg_txf_entries [2]), .I3(\spiflash_inst/u_spi_reg/n572_14 ), .F(\spiflash_inst/u_spi_reg/n578_13 ) ); defparam \spiflash_inst/u_spi_reg/n578_s9 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n580_s9 ( .I0(\spiflash_inst/arb_trans_ctrl [17]), .I1(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I2(\spiflash_inst/rxf_rd_data [17]), .I3(\spiflash_inst/reg_rd_a_Z_4 ), .F(\spiflash_inst/u_spi_reg/n580_13 ) ); defparam \spiflash_inst/u_spi_reg/n580_s9 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n580_s10 ( .I0(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I1(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [14]), .I2(\spiflash_inst/reg_txf_entries [1]), .I3(\spiflash_inst/u_spi_reg/n572_14 ), .F(\spiflash_inst/u_spi_reg/n580_14 ) ); defparam \spiflash_inst/u_spi_reg/n580_s10 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n580_s11 ( .I0(\spiflash_inst/arb_addr [17]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/arb_addr_len [1]), .I3(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .F(\spiflash_inst/u_spi_reg/n580_15 ) ); defparam \spiflash_inst/u_spi_reg/n580_s11 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n582_s9 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [16]), .I2(\spiflash_inst/reg_txf_entries [0]), .I3(\spiflash_inst/u_spi_reg/n572_14 ), .F(\spiflash_inst/u_spi_reg/n582_13 ) ); defparam \spiflash_inst/u_spi_reg/n582_s9 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n582_s10 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [13]), .I1(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I2(\spiflash_inst/arb_addr_len [0]), .I3(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .F(\spiflash_inst/u_spi_reg/n582_14 ) ); defparam \spiflash_inst/u_spi_reg/n582_s10 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n582_s11 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [16]), .I2(\spiflash_inst/arb_addr [16]), .I3(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .F(\spiflash_inst/u_spi_reg/n582_15 ) ); defparam \spiflash_inst/u_spi_reg/n582_s11 .INIT=16'h0777; LUT3 \spiflash_inst/u_spi_reg/n584_s9 ( .I0(\spiflash_inst/rxf_entries [0]), .I1(\spiflash_inst/rxf_entries [1]), .I2(\spiflash_inst/u_spi_reg/n584_16 ), .F(\spiflash_inst/u_spi_reg/n584_13 ) ); defparam \spiflash_inst/u_spi_reg/n584_s9 .INIT=8'h10; LUT4 \spiflash_inst/u_spi_reg/n584_s10 ( .I0(\spiflash_inst/arb_addr [15]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/rxf_rd_data [15]), .I3(\spiflash_inst/reg_rd_a_Z_4 ), .F(\spiflash_inst/u_spi_reg/n584_14 ) ); defparam \spiflash_inst/u_spi_reg/n584_s10 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n584_s11 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [15]), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [12]), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/n584_15 ) ); defparam \spiflash_inst/u_spi_reg/n584_s11 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n594_s10 ( .I0(\spiflash_inst/rxf_entries [2]), .I1(\spiflash_inst/u_spi_reg/n584_18 ), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [7]), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/n594_14 ) ); defparam \spiflash_inst/u_spi_reg/n594_s10 .INIT=16'h0777; LUT3 \spiflash_inst/u_spi_reg/n594_s11 ( .I0(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .I1(\spiflash_inst/spi_data_len [2]), .I2(\spiflash_inst/u_spi_reg/n594_17 ), .F(\spiflash_inst/u_spi_reg/n594_15 ) ); defparam \spiflash_inst/u_spi_reg/n594_s11 .INIT=8'h70; LUT4 \spiflash_inst/u_spi_reg/n594_s12 ( .I0(\spiflash_inst/arb_addr [10]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/arb_trans_ctrl [10]), .I3(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .F(\spiflash_inst/u_spi_reg/n594_16 ) ); defparam \spiflash_inst/u_spi_reg/n594_s12 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n602_s9 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [6]), .I2(\spiflash_inst/reg_spiif_setting [6]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n602_13 ) ); defparam \spiflash_inst/u_spi_reg/n602_s9 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n602_s10 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [6]), .I2(\spiflash_inst/arb_addr [6]), .I3(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .F(\spiflash_inst/u_spi_reg/n602_14 ) ); defparam \spiflash_inst/u_spi_reg/n602_s10 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n602_s11 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr_4 ), .I1(\spiflash_inst/arb_opcode [6]), .I2(I_paddr[6]), .I3(\spiflash_inst/u_spi_reg/n602_16 ), .F(\spiflash_inst/u_spi_reg/n602_15 ) ); defparam \spiflash_inst/u_spi_reg/n602_s11 .INIT=16'h0777; LUT3 \spiflash_inst/u_spi_reg/n556_s8 ( .I0(\spiflash_inst/arb_trans_ctrl [29]), .I1(\spiflash_inst/arb_addr [29]), .I2(I_paddr[3]), .F(\spiflash_inst/u_spi_reg/n556_12 ) ); defparam \spiflash_inst/u_spi_reg/n556_s8 .INIT=8'hCA; LUT2 \spiflash_inst/u_spi_reg/n556_s9 ( .I0(I_paddr[3]), .I1(\spiflash_inst/rxf_rd_data [29]), .F(\spiflash_inst/u_spi_reg/n556_13 ) ); defparam \spiflash_inst/u_spi_reg/n556_s9 .INIT=4'h8; LUT4 \spiflash_inst/u_spi_reg/n564_s8 ( .I0(\spiflash_inst/arb_addr [25]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/rxf_rd_data [25]), .I3(\spiflash_inst/reg_rd_a_Z_4 ), .F(\spiflash_inst/u_spi_reg/n564_12 ) ); defparam \spiflash_inst/u_spi_reg/n564_s8 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n566_s8 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [24]), .I2(\spiflash_inst/arb_addr [24]), .I3(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .F(\spiflash_inst/u_spi_reg/n566_12 ) ); defparam \spiflash_inst/u_spi_reg/n566_s8 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n568_s9 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I1(\spiflash_inst/arb_addr [23]), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [20]), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/n568_13 ) ); defparam \spiflash_inst/u_spi_reg/n568_s9 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n568_s10 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [23]), .I2(\spiflash_inst/reg_txf_full ), .I3(\spiflash_inst/u_spi_reg/n572_14 ), .F(\spiflash_inst/u_spi_reg/n568_14 ) ); defparam \spiflash_inst/u_spi_reg/n568_s10 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n570_s9 ( .I0(\spiflash_inst/reg_txf_entries [0]), .I1(\spiflash_inst/reg_txf_entries [1]), .I2(\spiflash_inst/u_spi_reg/n572_14 ), .I3(\spiflash_inst/u_spi_reg/n570_15 ), .F(\spiflash_inst/u_spi_reg/n570_13 ) ); defparam \spiflash_inst/u_spi_reg/n570_s9 .INIT=16'h1000; LUT4 \spiflash_inst/u_spi_reg/n570_s10 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [22]), .I2(\spiflash_inst/arb_addr [22]), .I3(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .F(\spiflash_inst/u_spi_reg/n570_14 ) ); defparam \spiflash_inst/u_spi_reg/n570_s10 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n586_s10 ( .I0(\spiflash_inst/reg_rd_a_Z_8 ), .I1(\spiflash_inst/u_spi_reg/n572_14 ), .I2(\spiflash_inst/arb_trans_ctrl [14]), .I3(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .F(\spiflash_inst/u_spi_reg/n586_14 ) ); defparam \spiflash_inst/u_spi_reg/n586_s10 .INIT=16'h0BBB; LUT4 \spiflash_inst/u_spi_reg/n586_s11 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [14]), .I2(\spiflash_inst/arb_addr [14]), .I3(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .F(\spiflash_inst/u_spi_reg/n586_15 ) ); defparam \spiflash_inst/u_spi_reg/n586_s11 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n588_s11 ( .I0(\spiflash_inst/u_spi_reg/rxf_thres_int_r_18 ), .I1(\spiflash_inst/u_spi_reg/n572_14 ), .I2(\spiflash_inst/arb_trans_ctrl [13]), .I3(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .F(\spiflash_inst/u_spi_reg/n588_15 ) ); defparam \spiflash_inst/u_spi_reg/n588_s11 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n588_s12 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [10]), .I1(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I2(\spiflash_inst/arb_addr [13]), .I3(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .F(\spiflash_inst/u_spi_reg/n588_16 ) ); defparam \spiflash_inst/u_spi_reg/n588_s12 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n588_s13 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [13]), .I2(\spiflash_inst/reg_spiif_setting [13]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n588_17 ) ); defparam \spiflash_inst/u_spi_reg/n588_s13 .INIT=16'h0777; LUT3 \spiflash_inst/u_spi_reg/n590_s12 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [12]), .I2(\spiflash_inst/u_spi_reg/n590_18 ), .F(\spiflash_inst/u_spi_reg/n590_16 ) ); defparam \spiflash_inst/u_spi_reg/n590_s12 .INIT=8'h70; LUT3 \spiflash_inst/u_spi_reg/n590_s13 ( .I0(\spiflash_inst/u_spi_reg/n584_18 ), .I1(\spiflash_inst/rxf_entries [4]), .I2(\spiflash_inst/u_spi_reg/n590_19 ), .F(\spiflash_inst/u_spi_reg/n590_17 ) ); defparam \spiflash_inst/u_spi_reg/n590_s13 .INIT=8'h70; LUT4 \spiflash_inst/u_spi_reg/n592_s12 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [11]), .I2(\spiflash_inst/reg_spiif_setting [11]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n592_16 ) ); defparam \spiflash_inst/u_spi_reg/n592_s12 .INIT=16'h0777; LUT3 \spiflash_inst/u_spi_reg/n592_s13 ( .I0(\spiflash_inst/u_spi_reg/n584_18 ), .I1(\spiflash_inst/rxf_entries [3]), .I2(\spiflash_inst/u_spi_reg/n592_19 ), .F(\spiflash_inst/u_spi_reg/n592_17 ) ); defparam \spiflash_inst/u_spi_reg/n592_s13 .INIT=8'h70; LUT4 \spiflash_inst/u_spi_reg/n592_s14 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [11]), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [8]), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/n592_18 ) ); defparam \spiflash_inst/u_spi_reg/n592_s14 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n596_s12 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I1(\spiflash_inst/arb_addr [9]), .I2(\spiflash_inst/u_spi_reg/n596_18 ), .I3(\spiflash_inst/u_spi_reg/n596_19 ), .F(\spiflash_inst/u_spi_reg/n596_16 ) ); defparam \spiflash_inst/u_spi_reg/n596_s12 .INIT=16'h7000; LUT4 \spiflash_inst/u_spi_reg/n596_s13 ( .I0(\spiflash_inst/rxf_entries [1]), .I1(\spiflash_inst/u_spi_reg/n584_18 ), .I2(\spiflash_inst/reg_spiif_setting [9]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n596_17 ) ); defparam \spiflash_inst/u_spi_reg/n596_s13 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n598_s12 ( .I0(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I1(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [5]), .I2(\spiflash_inst/reg_spiif_setting [8]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n598_16 ) ); defparam \spiflash_inst/u_spi_reg/n598_s12 .INIT=16'h0777; LUT3 \spiflash_inst/u_spi_reg/n598_s13 ( .I0(\spiflash_inst/u_spi_reg/n584_18 ), .I1(\spiflash_inst/rxf_entries [0]), .I2(\spiflash_inst/u_spi_reg/n598_19 ), .F(\spiflash_inst/u_spi_reg/n598_17 ) ); defparam \spiflash_inst/u_spi_reg/n598_s13 .INIT=8'h70; LUT4 \spiflash_inst/u_spi_reg/n598_s14 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [8]), .I2(\spiflash_inst/arb_addr [8]), .I3(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .F(\spiflash_inst/u_spi_reg/n598_18 ) ); defparam \spiflash_inst/u_spi_reg/n598_s14 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n600_s11 ( .I0(\spiflash_inst/arb_addr [7]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/reg_spi_format_r [5]), .I3(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .F(\spiflash_inst/u_spi_reg/n600_15 ) ); defparam \spiflash_inst/u_spi_reg/n600_s11 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n600_s12 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [7]), .I2(\spiflash_inst/arb_opcode [7]), .I3(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr_4 ), .F(\spiflash_inst/u_spi_reg/n600_16 ) ); defparam \spiflash_inst/u_spi_reg/n600_s12 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n600_s13 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [7]), .I2(\spiflash_inst/reg_spiif_setting [7]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n600_17 ) ); defparam \spiflash_inst/u_spi_reg/n600_s13 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n604_s12 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [5]), .I2(\spiflash_inst/arb_addr [5]), .I3(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .F(\spiflash_inst/u_spi_reg/n604_16 ) ); defparam \spiflash_inst/u_spi_reg/n604_s12 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n604_s13 ( .I0(\spiflash_inst/reg_spiif_setting [5]), .I1(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .I2(\spiflash_inst/arb_opcode [5]), .I3(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr_4 ), .F(\spiflash_inst/u_spi_reg/n604_17 ) ); defparam \spiflash_inst/u_spi_reg/n604_s13 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n606_s14 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [4]), .I2(\spiflash_inst/u_spi_reg/spi_trans_end_int_r ), .I3(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_11 ), .F(\spiflash_inst/u_spi_reg/n606_18 ) ); defparam \spiflash_inst/u_spi_reg/n606_s14 .INIT=16'h0777; LUT3 \spiflash_inst/u_spi_reg/n606_s15 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I1(\spiflash_inst/arb_addr [4]), .I2(\spiflash_inst/u_spi_reg/n606_22 ), .F(\spiflash_inst/u_spi_reg/n606_19 ) ); defparam \spiflash_inst/u_spi_reg/n606_s15 .INIT=8'h70; LUT4 \spiflash_inst/u_spi_reg/n606_s16 ( .I0(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .I1(\spiflash_inst/spi_3line ), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [4]), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/n606_20 ) ); defparam \spiflash_inst/u_spi_reg/n606_s16 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n606_s17 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr_4 ), .I1(\spiflash_inst/arb_opcode [4]), .I2(\spiflash_inst/u_spi_reg/reg_int_en_r [4]), .I3(\spiflash_inst/u_spi_reg/reg_int_en_wr_4 ), .F(\spiflash_inst/u_spi_reg/n606_21 ) ); defparam \spiflash_inst/u_spi_reg/n606_s17 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n608_s14 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [3]), .I1(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I2(\spiflash_inst/arb_opcode [3]), .I3(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr_4 ), .F(\spiflash_inst/u_spi_reg/n608_18 ) ); defparam \spiflash_inst/u_spi_reg/n608_s14 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n608_s15 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [3]), .I2(\spiflash_inst/reg_spiif_setting [3]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n608_19 ) ); defparam \spiflash_inst/u_spi_reg/n608_s15 .INIT=16'h0777; LUT3 \spiflash_inst/u_spi_reg/n608_s16 ( .I0(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .I1(\spiflash_inst/spi_lsb ), .I2(\spiflash_inst/u_spi_reg/n608_22 ), .F(\spiflash_inst/u_spi_reg/n608_20 ) ); defparam \spiflash_inst/u_spi_reg/n608_s16 .INIT=8'h70; LUT4 \spiflash_inst/u_spi_reg/n608_s17 ( .I0(\spiflash_inst/u_spi_reg/txf_thres_int_r ), .I1(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_11 ), .I2(\spiflash_inst/u_spi_reg/reg_int_en_r [3]), .I3(\spiflash_inst/u_spi_reg/reg_int_en_wr_4 ), .F(\spiflash_inst/u_spi_reg/n608_21 ) ); defparam \spiflash_inst/u_spi_reg/n608_s17 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n610_s14 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [2]), .I2(\spiflash_inst/reg_spiif_setting [2]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n610_18 ) ); defparam \spiflash_inst/u_spi_reg/n610_s14 .INIT=16'h0777; LUT3 \spiflash_inst/u_spi_reg/n610_s15 ( .I0(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I1(\spiflash_inst/txf_clr_level_Z ), .I2(\spiflash_inst/u_spi_reg/n610_22 ), .F(\spiflash_inst/u_spi_reg/n610_19 ) ); defparam \spiflash_inst/u_spi_reg/n610_s15 .INIT=8'h07; LUT4 \spiflash_inst/u_spi_reg/n610_s16 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [2]), .I2(\spiflash_inst/arb_opcode [2]), .I3(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr_4 ), .F(\spiflash_inst/u_spi_reg/n610_20 ) ); defparam \spiflash_inst/u_spi_reg/n610_s16 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n610_s17 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I1(\spiflash_inst/arb_addr [2]), .I2(\spiflash_inst/u_spi_reg/reg_int_en_r [2]), .I3(\spiflash_inst/u_spi_reg/reg_int_en_wr_4 ), .F(\spiflash_inst/u_spi_reg/n610_21 ) ); defparam \spiflash_inst/u_spi_reg/n610_s17 .INIT=16'h0777; LUT2 \spiflash_inst/u_spi_reg/n612_s14 ( .I0(\spiflash_inst/rxf_clr_level_Z ), .I1(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/n612_18 ) ); defparam \spiflash_inst/u_spi_reg/n612_s14 .INIT=4'h8; LUT4 \spiflash_inst/u_spi_reg/n612_s15 ( .I0(\spiflash_inst/reg_spiif_setting [1]), .I1(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .I2(\spiflash_inst/arb_opcode [1]), .I3(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr_4 ), .F(\spiflash_inst/u_spi_reg/n612_19 ) ); defparam \spiflash_inst/u_spi_reg/n612_s15 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n612_s16 ( .I0(\spiflash_inst/arb_trans_ctrl [1]), .I1(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I2(\spiflash_inst/rxf_rd_data [1]), .I3(\spiflash_inst/reg_rd_a_Z_4 ), .F(\spiflash_inst/u_spi_reg/n612_20 ) ); defparam \spiflash_inst/u_spi_reg/n612_s16 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n612_s17 ( .I0(\spiflash_inst/arb_addr [1]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/spi_mode [1]), .I3(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .F(\spiflash_inst/u_spi_reg/n612_21 ) ); defparam \spiflash_inst/u_spi_reg/n612_s17 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n613_s15 ( .I0(\spiflash_inst/ctrl_word_len_0_7 ), .I1(\spiflash_inst/arb_busy_sysclk ), .I2(\spiflash_inst/n74_7 ), .I3(\spiflash_inst/u_spi_reg/n572_14 ), .F(\spiflash_inst/u_spi_reg/n613_19 ) ); defparam \spiflash_inst/u_spi_reg/n613_s15 .INIT=16'hF800; LUT4 \spiflash_inst/u_spi_reg/n613_s16 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr_4 ), .I1(\spiflash_inst/arb_opcode [0]), .I2(\spiflash_inst/spi_reset_sysclk_Z ), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_reg/n613_20 ) ); defparam \spiflash_inst/u_spi_reg/n613_s16 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n613_s17 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [0]), .I2(\spiflash_inst/u_spi_reg/n613_22 ), .I3(\spiflash_inst/u_spi_reg/n613_23 ), .F(\spiflash_inst/u_spi_reg/n613_21 ) ); defparam \spiflash_inst/u_spi_reg/n613_s17 .INIT=16'h7000; LUT3 \spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_s2 ( .I0(I_paddr[6]), .I1(I_paddr[5]), .I2(I_paddr[4]), .F(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_5 ) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_s2 .INIT=8'h40; LUT2 \spiflash_inst/u_spi_reg/spi_trans_end_int_r_s6 ( .I0(I_paddr[6]), .I1(\spiflash_inst/u_spi_reg/n602_16 ), .F(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_11 ) ); defparam \spiflash_inst/u_spi_reg/spi_trans_end_int_r_s6 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_reg/rxf_thres_int_r_s5 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [9]), .I1(\spiflash_inst/u_spi_reg/rxf_thres_int_r_13 ), .I2(\spiflash_inst/ctrl_word_len_0_7 ), .I3(\spiflash_inst/rxf_entries [4]), .F(\spiflash_inst/u_spi_reg/rxf_thres_int_r_10 ) ); defparam \spiflash_inst/u_spi_reg/rxf_thres_int_r_s5 .INIT=16'h8EEE; LUT3 \spiflash_inst/u_spi_reg/rxf_thres_int_r_s7 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [12]), .I1(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [11]), .I2(\spiflash_inst/u_spi_reg/reg_int_en_r [2]), .F(\spiflash_inst/u_spi_reg/rxf_thres_int_r_12 ) ); defparam \spiflash_inst/u_spi_reg/rxf_thres_int_r_s7 .INIT=8'h10; LUT3 \spiflash_inst/u_spi_reg/n572_s10 ( .I0(I_paddr[3]), .I1(I_paddr[2]), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_5 ), .F(\spiflash_inst/u_spi_reg/n572_14 ) ); defparam \spiflash_inst/u_spi_reg/n572_s10 .INIT=8'h40; LUT4 \spiflash_inst/u_spi_reg/n584_s12 ( .I0(\spiflash_inst/rxf_entries [2]), .I1(\spiflash_inst/rxf_entries [3]), .I2(\spiflash_inst/rxf_entries [4]), .I3(\spiflash_inst/rxf_entries [5]), .F(\spiflash_inst/u_spi_reg/n584_16 ) ); defparam \spiflash_inst/u_spi_reg/n584_s12 .INIT=16'h0100; LUT4 \spiflash_inst/u_spi_reg/n594_s13 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [10]), .I2(\spiflash_inst/reg_spiif_setting [10]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n594_17 ) ); defparam \spiflash_inst/u_spi_reg/n594_s13 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n602_s12 ( .I0(I_paddr[2]), .I1(I_paddr[3]), .I2(I_paddr[4]), .I3(I_paddr[5]), .F(\spiflash_inst/u_spi_reg/n602_16 ) ); defparam \spiflash_inst/u_spi_reg/n602_s12 .INIT=16'h8000; LUT4 \spiflash_inst/u_spi_reg/n570_s11 ( .I0(\spiflash_inst/reg_txf_entries [2]), .I1(\spiflash_inst/reg_txf_entries [3]), .I2(\spiflash_inst/reg_txf_entries [4]), .I3(\spiflash_inst/reg_txf_entries [5]), .F(\spiflash_inst/u_spi_reg/n570_15 ) ); defparam \spiflash_inst/u_spi_reg/n570_s11 .INIT=16'h0001; LUT4 \spiflash_inst/u_spi_reg/n590_s14 ( .I0(\spiflash_inst/arb_addr [12]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/rxf_rd_data [12]), .I3(\spiflash_inst/reg_rd_a_Z_4 ), .F(\spiflash_inst/u_spi_reg/n590_18 ) ); defparam \spiflash_inst/u_spi_reg/n590_s14 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n590_s15 ( .I0(\spiflash_inst/reg_spiif_setting [12]), .I1(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .I2(\spiflash_inst/spi_data_len [4]), .I3(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .F(\spiflash_inst/u_spi_reg/n590_19 ) ); defparam \spiflash_inst/u_spi_reg/n590_s15 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n592_s15 ( .I0(\spiflash_inst/arb_addr [11]), .I1(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .I2(\spiflash_inst/spi_data_len [3]), .I3(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .F(\spiflash_inst/u_spi_reg/n592_19 ) ); defparam \spiflash_inst/u_spi_reg/n592_s15 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n596_s14 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [6]), .I1(\spiflash_inst/reg_reg_ctrl_wr_7 ), .I2(\spiflash_inst/arb_trans_ctrl [9]), .I3(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .F(\spiflash_inst/u_spi_reg/n596_18 ) ); defparam \spiflash_inst/u_spi_reg/n596_s14 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n596_s15 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [9]), .I2(\spiflash_inst/spi_data_len [1]), .I3(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .F(\spiflash_inst/u_spi_reg/n596_19 ) ); defparam \spiflash_inst/u_spi_reg/n596_s15 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n598_s15 ( .I0(\spiflash_inst/arb_trans_ctrl [8]), .I1(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I2(\spiflash_inst/spi_data_len [0]), .I3(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .F(\spiflash_inst/u_spi_reg/n598_19 ) ); defparam \spiflash_inst/u_spi_reg/n598_s15 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n606_s18 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ), .I1(\spiflash_inst/arb_trans_ctrl [4]), .I2(\spiflash_inst/reg_spiif_setting [4]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n606_22 ) ); defparam \spiflash_inst/u_spi_reg/n606_s18 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n608_s18 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [3]), .I2(\spiflash_inst/arb_addr [3]), .I3(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .F(\spiflash_inst/u_spi_reg/n608_22 ) ); defparam \spiflash_inst/u_spi_reg/n608_s18 .INIT=16'h0777; LUT3 \spiflash_inst/u_spi_reg/n610_s18 ( .I0(\spiflash_inst/u_spi_reg/rxf_thres_int_r ), .I1(I_paddr[6]), .I2(\spiflash_inst/u_spi_reg/n602_16 ), .F(\spiflash_inst/u_spi_reg/n610_22 ) ); defparam \spiflash_inst/u_spi_reg/n610_s18 .INIT=8'hE0; LUT4 \spiflash_inst/u_spi_reg/n613_s18 ( .I0(\spiflash_inst/reg_rd_a_Z_4 ), .I1(\spiflash_inst/rxf_rd_data [0]), .I2(\spiflash_inst/arb_addr [0]), .I3(\spiflash_inst/u_spi_reg/reg_reg_addr_wr_4 ), .F(\spiflash_inst/u_spi_reg/n613_22 ) ); defparam \spiflash_inst/u_spi_reg/n613_s18 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/n613_s19 ( .I0(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .I1(\spiflash_inst/spi_mode [0]), .I2(\spiflash_inst/reg_spiif_setting [0]), .I3(\spiflash_inst/u_spi_reg/reg_spi_interface_wr_4 ), .F(\spiflash_inst/u_spi_reg/n613_23 ) ); defparam \spiflash_inst/u_spi_reg/n613_s19 .INIT=16'h0777; LUT4 \spiflash_inst/u_spi_reg/rxf_thres_int_r_s8 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [8]), .I1(\spiflash_inst/u_spi_reg/rxf_thres_int_r_14 ), .I2(\spiflash_inst/ctrl_word_len_0_7 ), .I3(\spiflash_inst/rxf_entries [3]), .F(\spiflash_inst/u_spi_reg/rxf_thres_int_r_13 ) ); defparam \spiflash_inst/u_spi_reg/rxf_thres_int_r_s8 .INIT=16'h2BBB; LUT4 \spiflash_inst/u_spi_reg/rxf_thres_int_r_s9 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [7]), .I1(\spiflash_inst/u_spi_reg/rxf_thres_int_r_15 ), .I2(\spiflash_inst/rxf_entries [2]), .I3(\spiflash_inst/u_spi_reg/rxf_thres_int_r_16 ), .F(\spiflash_inst/u_spi_reg/rxf_thres_int_r_14 ) ); defparam \spiflash_inst/u_spi_reg/rxf_thres_int_r_s9 .INIT=16'h00D4; LUT4 \spiflash_inst/u_spi_reg/rxf_thres_int_r_s10 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [6]), .I1(\spiflash_inst/rxf_entries [1]), .I2(\spiflash_inst/rxf_entries [0]), .I3(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [5]), .F(\spiflash_inst/u_spi_reg/rxf_thres_int_r_15 ) ); defparam \spiflash_inst/u_spi_reg/rxf_thres_int_r_s10 .INIT=16'hD4DD; LUT4 \spiflash_inst/u_spi_reg/rxf_thres_int_r_s11 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [6]), .I1(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [5]), .I2(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [7]), .I3(\spiflash_inst/ctrl_word_len_0_7 ), .F(\spiflash_inst/u_spi_reg/rxf_thres_int_r_16 ) ); defparam \spiflash_inst/u_spi_reg/rxf_thres_int_r_s11 .INIT=16'h00FE; LUT4 \spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_s3 ( .I0(\spiflash_inst/u_spi_reg/n554_10 ), .I1(I_paddr[6]), .I2(I_paddr[5]), .I3(I_paddr[4]), .F(\spiflash_inst/reg_reg_ctrl_wr_7 ) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_s3 .INIT=16'h2000; LUT3 \spiflash_inst/u_spi_reg/spi_trans_end_int_r_s7 ( .I0(\spiflash_inst/reg_spi_format_wr_4 ), .I1(I_paddr[6]), .I2(\spiflash_inst/u_spi_reg/n602_16 ), .F(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_13 ) ); defparam \spiflash_inst/u_spi_reg/spi_trans_end_int_r_s7 .INIT=8'h20; LUT4 \spiflash_inst/u_spi_reg/reg_int_en_wr_s2 ( .I0(\spiflash_inst/reg_spi_format_wr_4 ), .I1(I_paddr[2]), .I2(I_paddr[3]), .I3(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_5 ), .F(\spiflash_inst/u_spi_reg/reg_int_en_wr ) ); defparam \spiflash_inst/u_spi_reg/reg_int_en_wr_s2 .INIT=16'h2000; LUT3 \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_s2 ( .I0(\spiflash_inst/n554_12 ), .I1(I_paddr[2]), .I2(I_paddr[3]), .F(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_6 ) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_s2 .INIT=8'h02; LUT4 \spiflash_inst/u_spi_reg/reg_reg_cmd_wr_s2 ( .I0(\spiflash_inst/reg_spi_format_wr_4 ), .I1(I_paddr[3]), .I2(I_paddr[2]), .I3(\spiflash_inst/n554_12 ), .F(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr ) ); defparam \spiflash_inst/u_spi_reg/reg_reg_cmd_wr_s2 .INIT=16'h2000; LUT3 \spiflash_inst/u_spi_reg/spi_mode_r_1_s4 ( .I0(\spiflash_inst/u_spi_reg/spi_rstn_d2_r ), .I1(\spiflash_inst/reg_spi_format_wr_4 ), .I2(\spiflash_inst/u_spi_reg/reg_spi_format_wr_5 ), .F(\spiflash_inst/u_spi_reg/spi_mode_r_1_8 ) ); defparam \spiflash_inst/u_spi_reg/spi_mode_r_1_s4 .INIT=8'hEA; LUT4 \spiflash_inst/u_spi_reg/n584_s13 ( .I0(\spiflash_inst/ctrl_word_len_0_7 ), .I1(I_paddr[3]), .I2(I_paddr[2]), .I3(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr_5 ), .F(\spiflash_inst/u_spi_reg/n584_18 ) ); defparam \spiflash_inst/u_spi_reg/n584_s13 .INIT=16'h2000; LUT3 \spiflash_inst/u_spi_reg/rxf_thres_int_r_s12 ( .I0(\spiflash_inst/rxf_entries [5]), .I1(\spiflash_inst/arb_cs_r [1]), .I2(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/u_spi_reg/rxf_thres_int_r_18 ) ); defparam \spiflash_inst/u_spi_reg/rxf_thres_int_r_s12 .INIT=8'h02; LUT4 \spiflash_inst/u_spi_reg/spi_trans_end_int_r_s8 ( .I0(\spiflash_inst/a_level_sync2b_syn2_r ), .I1(\spiflash_inst/a_level_sync2b_syn3_r ), .I2(\spiflash_inst/arb_cs_r [1]), .I3(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/spi_trans_end_int_r_15 ) ); defparam \spiflash_inst/u_spi_reg/spi_trans_end_int_r_s8 .INIT=16'h0006; LUT3 \spiflash_inst/u_spi_reg/reg_txf_clr_regclk_Z_s0 ( .I0(I_pwdata[2]), .I1(\spiflash_inst/reg_spi_format_wr_4 ), .I2(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/reg_txf_clr_regclk_Z ) ); defparam \spiflash_inst/u_spi_reg/reg_txf_clr_regclk_Z_s0 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_reg/spi_reset_regclk_Z_s0 ( .I0(I_pwdata[0]), .I1(\spiflash_inst/reg_spi_format_wr_4 ), .I2(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/spi_reset_regclk_Z ) ); defparam \spiflash_inst/u_spi_reg/spi_reset_regclk_Z_s0 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_reg/reg_reg_addr_wr_s2 ( .I0(\spiflash_inst/reg_spi_format_wr_4 ), .I1(I_paddr[2]), .I2(I_paddr[3]), .I3(\spiflash_inst/n554_12 ), .F(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_wr_s2 .INIT=16'h2000; LUT4 \spiflash_inst/u_spi_reg/n220_s4 ( .I0(\spiflash_inst/spi_reset_sysclk_Z ), .I1(I_pwdata[1]), .I2(\spiflash_inst/reg_spi_format_wr_4 ), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/n220_9 ) ); defparam \spiflash_inst/u_spi_reg/n220_s4 .INIT=16'h1555; LUT4 \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_s3 ( .I0(\spiflash_inst/reg_spi_format_wr_4 ), .I1(\spiflash_inst/n554_12 ), .I2(I_paddr[2]), .I3(I_paddr[3]), .F(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr_s3 .INIT=16'h0008; DFFPE \spiflash_inst/u_spi_reg/spi_rstn_d2_r_s0 ( .D(\spiflash_inst/u_spi_reg/spi_rstn_d1_r ), .CLK(I_pclk), .CE(VCC), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/spi_rstn_d2_r ) ); defparam \spiflash_inst/u_spi_reg/spi_rstn_d2_r_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spi_format_r_12_s0 ( .D(I_pwdata[17]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_format_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr_len [1]) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_r_12_s0 .INIT=1'b1; DFFCE \spiflash_inst/u_spi_reg/reg_spi_format_r_11_s0 ( .D(I_pwdata[16]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_format_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr_len [0]) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_r_11_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_spi_format_r_10_s0 ( .D(I_pwdata[12]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_format_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/spi_data_len [4]) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_r_10_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_spi_format_r_9_s0 ( .D(I_pwdata[11]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_format_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/spi_data_len [3]) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_r_9_s0 .INIT=1'b0; DFFPE \spiflash_inst/u_spi_reg/reg_spi_format_r_8_s0 ( .D(I_pwdata[10]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_format_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/spi_data_len [2]) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_r_8_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spi_format_r_7_s0 ( .D(I_pwdata[9]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_format_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/spi_data_len [1]) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_r_7_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spi_format_r_6_s0 ( .D(I_pwdata[8]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_format_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/spi_data_len [0]) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_r_6_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spi_format_r_5_s0 ( .D(I_pwdata[7]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_format_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spi_format_r [5]) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_r_5_s0 .INIT=1'b1; DFFCE \spiflash_inst/u_spi_reg/reg_spi_format_r_4_s0 ( .D(I_pwdata[4]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_format_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/spi_3line ) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_r_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_spi_format_r_3_s0 ( .D(I_pwdata[3]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_format_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/spi_lsb ) ); defparam \spiflash_inst/u_spi_reg/reg_spi_format_r_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_30_s0 ( .D(I_pwdata[30]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [30]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_30_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_29_s0 ( .D(I_pwdata[29]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [29]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_29_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_27_s0 ( .D(I_pwdata[27]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [27]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_27_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_26_s0 ( .D(I_pwdata[26]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [26]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_26_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_25_s0 ( .D(I_pwdata[25]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [25]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_25_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_24_s0 ( .D(I_pwdata[24]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [24]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_24_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_21_s0 ( .D(I_pwdata[21]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [21]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_21_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_20_s0 ( .D(I_pwdata[20]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [20]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_20_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_19_s0 ( .D(I_pwdata[19]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [19]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_19_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_18_s0 ( .D(I_pwdata[18]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [18]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_18_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_17_s0 ( .D(I_pwdata[17]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [17]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_17_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_16_s0 ( .D(I_pwdata[16]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [16]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_16_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_15_s0 ( .D(I_pwdata[15]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [15]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_15_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_14_s0 ( .D(I_pwdata[14]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [14]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_14_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_13_s0 ( .D(I_pwdata[13]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [13]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_13_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_12_s0 ( .D(I_pwdata[12]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [12]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_12_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_11_s0 ( .D(I_pwdata[11]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [11]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_11_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_10_s0 ( .D(I_pwdata[10]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [10]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_10_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_9_s0 ( .D(I_pwdata[9]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [9]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_9_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_8_s0 ( .D(I_pwdata[8]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [8]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_8_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_7_s0 ( .D(I_pwdata[7]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [7]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_7_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_6_s0 ( .D(I_pwdata[6]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [6]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_6_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_5_s0 ( .D(I_pwdata[5]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [5]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_4_s0 ( .D(I_pwdata[4]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [4]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_3_s0 ( .D(I_pwdata[3]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [3]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_2_s0 ( .D(I_pwdata[2]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [2]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_1_s0 ( .D(I_pwdata[1]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [1]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_0_s0 ( .D(I_pwdata[0]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_trans_ctrl [0]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_tra_ctrl_r_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_cmd_r_7_s0 ( .D(I_pwdata[7]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_opcode [7]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_cmd_r_7_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_cmd_r_6_s0 ( .D(I_pwdata[6]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_opcode [6]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_cmd_r_6_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_cmd_r_5_s0 ( .D(I_pwdata[5]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_opcode [5]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_cmd_r_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_cmd_r_4_s0 ( .D(I_pwdata[4]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_opcode [4]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_cmd_r_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_cmd_r_3_s0 ( .D(I_pwdata[3]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_opcode [3]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_cmd_r_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_cmd_r_2_s0 ( .D(I_pwdata[2]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_opcode [2]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_cmd_r_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_cmd_r_1_s0 ( .D(I_pwdata[1]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_opcode [1]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_cmd_r_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_cmd_r_0_s0 ( .D(I_pwdata[0]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_cmd_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_opcode [0]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_cmd_r_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_31_s0 ( .D(I_pwdata[31]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [31]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_31_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_30_s0 ( .D(I_pwdata[30]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [30]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_30_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_29_s0 ( .D(I_pwdata[29]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [29]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_29_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_28_s0 ( .D(I_pwdata[28]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [28]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_28_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_27_s0 ( .D(I_pwdata[27]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [27]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_27_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_26_s0 ( .D(I_pwdata[26]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [26]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_26_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_25_s0 ( .D(I_pwdata[25]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [25]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_25_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_24_s0 ( .D(I_pwdata[24]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [24]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_24_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_23_s0 ( .D(I_pwdata[23]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [23]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_23_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_22_s0 ( .D(I_pwdata[22]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [22]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_22_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_21_s0 ( .D(I_pwdata[21]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [21]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_21_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_20_s0 ( .D(I_pwdata[20]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [20]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_20_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_19_s0 ( .D(I_pwdata[19]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [19]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_19_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_18_s0 ( .D(I_pwdata[18]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [18]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_18_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_17_s0 ( .D(I_pwdata[17]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [17]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_17_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_16_s0 ( .D(I_pwdata[16]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [16]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_16_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_15_s0 ( .D(I_pwdata[15]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [15]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_15_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_14_s0 ( .D(I_pwdata[14]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [14]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_14_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_13_s0 ( .D(I_pwdata[13]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [13]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_13_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_12_s0 ( .D(I_pwdata[12]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [12]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_12_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_11_s0 ( .D(I_pwdata[11]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [11]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_11_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_10_s0 ( .D(I_pwdata[10]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [10]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_10_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_9_s0 ( .D(I_pwdata[9]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [9]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_9_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_8_s0 ( .D(I_pwdata[8]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [8]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_8_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_7_s0 ( .D(I_pwdata[7]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [7]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_7_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_6_s0 ( .D(I_pwdata[6]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [6]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_6_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_5_s0 ( .D(I_pwdata[5]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [5]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_4_s0 ( .D(I_pwdata[4]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [4]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_3_s0 ( .D(I_pwdata[3]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [3]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_2_s0 ( .D(I_pwdata[2]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [2]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_1_s0 ( .D(I_pwdata[1]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [1]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_addr_r_0_s0 ( .D(I_pwdata[0]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_addr_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_addr [0]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_addr_r_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_20_s0 ( .D(I_pwdata[23]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [20]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_20_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_19_s0 ( .D(I_pwdata[22]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [19]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_19_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_18_s0 ( .D(I_pwdata[21]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [18]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_18_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_17_s0 ( .D(I_pwdata[20]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [17]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_17_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_16_s0 ( .D(I_pwdata[19]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [16]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_16_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_15_s0 ( .D(I_pwdata[18]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [15]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_15_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_14_s0 ( .D(I_pwdata[17]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [14]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_14_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_13_s0 ( .D(I_pwdata[16]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [13]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_13_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_12_s0 ( .D(I_pwdata[15]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [12]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_12_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_11_s0 ( .D(I_pwdata[14]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [11]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_11_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_10_s0 ( .D(I_pwdata[13]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [10]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_10_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_9_s0 ( .D(I_pwdata[12]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [9]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_9_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_8_s0 ( .D(I_pwdata[11]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [8]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_8_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_7_s0 ( .D(I_pwdata[10]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [7]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_7_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_6_s0 ( .D(I_pwdata[9]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [6]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_6_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_5_s0 ( .D(I_pwdata[8]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [5]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_4_s0 ( .D(I_pwdata[4]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [4]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_3_s0 ( .D(I_pwdata[3]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_reg_ctrl_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [3]) ); defparam \spiflash_inst/u_spi_reg/reg_reg_ctrl_r_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_int_en_r_4_s0 ( .D(I_pwdata[4]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_int_en_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_int_en_r [4]) ); defparam \spiflash_inst/u_spi_reg/reg_int_en_r_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_int_en_r_3_s0 ( .D(I_pwdata[3]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_int_en_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_int_en_r [3]) ); defparam \spiflash_inst/u_spi_reg/reg_int_en_r_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_int_en_r_2_s0 ( .D(I_pwdata[2]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_int_en_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/reg_int_en_r [2]) ); defparam \spiflash_inst/u_spi_reg/reg_int_en_r_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_13_s0 ( .D(I_pwdata[13]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [13]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_13_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_12_s0 ( .D(I_pwdata[12]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [12]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_12_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_11_s0 ( .D(I_pwdata[11]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [11]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_11_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_10_s0 ( .D(I_pwdata[10]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [10]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_10_s0 .INIT=1'b0; DFFPE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_9_s0 ( .D(I_pwdata[9]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [9]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_9_s0 .INIT=1'b1; DFFCE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_8_s0 ( .D(I_pwdata[8]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [8]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_8_s0 .INIT=1'b0; DFFPE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_7_s0 ( .D(I_pwdata[7]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [7]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_7_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_6_s0 ( .D(I_pwdata[6]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [6]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_6_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_5_s0 ( .D(I_pwdata[5]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [5]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_5_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_4_s0 ( .D(I_pwdata[4]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [4]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_4_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_3_s0 ( .D(I_pwdata[3]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [3]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_3_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_2_s0 ( .D(I_pwdata[2]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [2]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_2_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_1_s0 ( .D(I_pwdata[1]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [1]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_1_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0 ( .D(I_pwdata[0]), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_spi_interface_wr ), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_spiif_setting [0]) ); defparam \spiflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0 .INIT=1'b1; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_31_s0 ( .D(\spiflash_inst/u_spi_reg/n552_10 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[31]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_31_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_30_s0 ( .D(\spiflash_inst/u_spi_reg/n554_9 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[30]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_30_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_29_s0 ( .D(\spiflash_inst/u_spi_reg/n556_11 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[29]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_29_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_28_s0 ( .D(\spiflash_inst/u_spi_reg/n558_13 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[28]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_28_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_27_s0 ( .D(\spiflash_inst/u_spi_reg/n560_9 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[27]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_27_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_26_s0 ( .D(\spiflash_inst/u_spi_reg/n562_9 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[26]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_26_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_25_s0 ( .D(\spiflash_inst/u_spi_reg/n564_11 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[25]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_25_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_24_s0 ( .D(\spiflash_inst/u_spi_reg/n566_11 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[24]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_24_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_23_s0 ( .D(\spiflash_inst/u_spi_reg/n568_12 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[23]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_23_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_22_s0 ( .D(\spiflash_inst/u_spi_reg/n570_12 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[22]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_22_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_21_s0 ( .D(\spiflash_inst/u_spi_reg/n572_11 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[21]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_21_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_20_s0 ( .D(\spiflash_inst/u_spi_reg/n574_11 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[20]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_20_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_19_s0 ( .D(\spiflash_inst/u_spi_reg/n576_11 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[19]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_19_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_18_s0 ( .D(\spiflash_inst/u_spi_reg/n578_11 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[18]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_18_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_17_s0 ( .D(\spiflash_inst/u_spi_reg/n580_12 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[17]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_17_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_16_s0 ( .D(\spiflash_inst/u_spi_reg/n582_12 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[16]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_16_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_15_s0 ( .D(\spiflash_inst/u_spi_reg/n584_11 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[15]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_15_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_14_s0 ( .D(\spiflash_inst/u_spi_reg/n586_13 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[14]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_14_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_13_s0 ( .D(\spiflash_inst/u_spi_reg/n588_14 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[13]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_13_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_12_s0 ( .D(\spiflash_inst/u_spi_reg/n590_15 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[12]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_12_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_11_s0 ( .D(\spiflash_inst/u_spi_reg/n592_15 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[11]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_11_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_10_s0 ( .D(\spiflash_inst/u_spi_reg/n594_13 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[10]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_10_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_9_s0 ( .D(\spiflash_inst/u_spi_reg/n596_15 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[9]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_9_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_8_s0 ( .D(\spiflash_inst/u_spi_reg/n598_15 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[8]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_8_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_7_s0 ( .D(\spiflash_inst/u_spi_reg/n600_14 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[7]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_7_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_6_s0 ( .D(\spiflash_inst/u_spi_reg/n602_12 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[6]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_6_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_5_s0 ( .D(\spiflash_inst/u_spi_reg/n604_15 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[5]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_4_s0 ( .D(\spiflash_inst/u_spi_reg/n606_17 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[4]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_3_s0 ( .D(\spiflash_inst/u_spi_reg/n608_17 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[3]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_2_s0 ( .D(\spiflash_inst/u_spi_reg/n610_17 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[2]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_1_s0 ( .D(\spiflash_inst/u_spi_reg/n612_17 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[1]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_rdata_r_0_s0 ( .D(\spiflash_inst/u_spi_reg/n613_18 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rd_a_Z ), .CLEAR(\spiflash_inst/n11_6 ), .Q(O_prdata[0]) ); defparam \spiflash_inst/u_spi_reg/reg_rdata_r_0_s0 .INIT=1'b0; DFFPE \spiflash_inst/u_spi_reg/spi_rstn_d1_r_s0 ( .D(GND), .CLK(I_pclk), .CE(VCC), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/spi_rstn_d1_r ) ); defparam \spiflash_inst/u_spi_reg/spi_rstn_d1_r_s0 .INIT=1'b1; DFFCE \spiflash_inst/u_spi_reg/spi_mode_r_1_s1 ( .D(\spiflash_inst/u_spi_reg/n87_6 ), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/spi_mode_r_1_8 ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/spi_mode [1]) ); defparam \spiflash_inst/u_spi_reg/spi_mode_r_1_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/spi_mode_r_0_s1 ( .D(\spiflash_inst/u_spi_reg/n88_6 ), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/spi_mode_r_1_8 ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/spi_mode [0]) ); defparam \spiflash_inst/u_spi_reg/spi_mode_r_0_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/reg_req_r_s1 ( .D(\spiflash_inst/u_spi_reg/n220_6 ), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/reg_req_r_8 ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/reg_req_r ) ); defparam \spiflash_inst/u_spi_reg/reg_req_r_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/spi_trans_end_int_r_s1 ( .D(\spiflash_inst/u_spi_reg/n418_7 ), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/spi_trans_end_int_r_8 ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/spi_trans_end_int_r ) ); defparam \spiflash_inst/u_spi_reg/spi_trans_end_int_r_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/txf_thres_int_r_s1 ( .D(\spiflash_inst/u_spi_reg/n430_7 ), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/txf_thres_int_r_8 ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/txf_thres_int_r ) ); defparam \spiflash_inst/u_spi_reg/txf_thres_int_r_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_reg/rxf_thres_int_r_s1 ( .D(\spiflash_inst/u_spi_reg/n440_7 ), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_reg/rxf_thres_int_r_8 ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_reg/rxf_thres_int_r ) ); defparam \spiflash_inst/u_spi_reg/rxf_thres_int_r_s1 .INIT=1'b0; ALU \spiflash_inst/u_spi_reg/txf_threshold_trigger_s18 ( .I0(VCC), .I1(\spiflash_inst/reg_txf_entries [0]), .I3(GND), .CIN(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [13]), .COUT(\spiflash_inst/u_spi_reg/txf_threshold_trigger_21 ), .SUM(\spiflash_inst/u_spi_reg/txf_threshold_trigger_19_SUM ) ); defparam \spiflash_inst/u_spi_reg/txf_threshold_trigger_s18 .ALU_MODE=1; ALU \spiflash_inst/u_spi_reg/txf_threshold_trigger_s19 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [14]), .I1(\spiflash_inst/reg_txf_entries [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_reg/txf_threshold_trigger_21 ), .COUT(\spiflash_inst/u_spi_reg/txf_threshold_trigger_23 ), .SUM(\spiflash_inst/u_spi_reg/txf_threshold_trigger_20_SUM ) ); defparam \spiflash_inst/u_spi_reg/txf_threshold_trigger_s19 .ALU_MODE=1; ALU \spiflash_inst/u_spi_reg/txf_threshold_trigger_s20 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [15]), .I1(\spiflash_inst/reg_txf_entries [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_reg/txf_threshold_trigger_23 ), .COUT(\spiflash_inst/u_spi_reg/txf_threshold_trigger_25 ), .SUM(\spiflash_inst/u_spi_reg/txf_threshold_trigger_21_SUM ) ); defparam \spiflash_inst/u_spi_reg/txf_threshold_trigger_s20 .ALU_MODE=1; ALU \spiflash_inst/u_spi_reg/txf_threshold_trigger_s21 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [16]), .I1(\spiflash_inst/reg_txf_entries [3]), .I3(GND), .CIN(\spiflash_inst/u_spi_reg/txf_threshold_trigger_25 ), .COUT(\spiflash_inst/u_spi_reg/txf_threshold_trigger_27 ), .SUM(\spiflash_inst/u_spi_reg/txf_threshold_trigger_22_SUM ) ); defparam \spiflash_inst/u_spi_reg/txf_threshold_trigger_s21 .ALU_MODE=1; ALU \spiflash_inst/u_spi_reg/txf_threshold_trigger_s22 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [17]), .I1(\spiflash_inst/reg_txf_entries [4]), .I3(GND), .CIN(\spiflash_inst/u_spi_reg/txf_threshold_trigger_27 ), .COUT(\spiflash_inst/u_spi_reg/txf_threshold_trigger_29 ), .SUM(\spiflash_inst/u_spi_reg/txf_threshold_trigger_23_SUM ) ); defparam \spiflash_inst/u_spi_reg/txf_threshold_trigger_s22 .ALU_MODE=1; ALU \spiflash_inst/u_spi_reg/txf_threshold_trigger_s23 ( .I0(\spiflash_inst/u_spi_reg/reg_reg_ctrl_r [18]), .I1(\spiflash_inst/reg_txf_entries [5]), .I3(GND), .CIN(\spiflash_inst/u_spi_reg/txf_threshold_trigger_29 ), .COUT(\spiflash_inst/u_spi_reg/txf_threshold_trigger_31 ), .SUM(\spiflash_inst/u_spi_reg/txf_threshold_trigger_24_SUM ) ); defparam \spiflash_inst/u_spi_reg/txf_threshold_trigger_s23 .ALU_MODE=1; LUT2 \spiflash_inst/u_spi_arbiter/n75_s2 ( .I0(\spiflash_inst/spi_reset_sysclk_Z ), .I1(\spiflash_inst/u_spi_arbiter/n75_7 ), .F(\spiflash_inst/u_spi_arbiter/n75_6 ) ); defparam \spiflash_inst/u_spi_arbiter/n75_s2 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_arbiter/n74_s2 ( .I0(\spiflash_inst/n74_7 ), .I1(\spiflash_inst/arb_cs_r [1]), .I2(\spiflash_inst/spi_reset_sysclk_Z ), .I3(\spiflash_inst/u_spi_arbiter/n74_8 ), .F(\spiflash_inst/u_spi_arbiter/n74_6 ) ); defparam \spiflash_inst/u_spi_arbiter/n74_s2 .INIT=16'h070C; LUT4 \spiflash_inst/u_spi_arbiter/n73_s2 ( .I0(\spiflash_inst/u_spi_arbiter/n73_10 ), .I1(\spiflash_inst/n74_7 ), .I2(\spiflash_inst/spi_reset_sysclk_Z ), .I3(\spiflash_inst/u_spi_arbiter/n73_8 ), .F(\spiflash_inst/u_spi_arbiter/n73_6 ) ); defparam \spiflash_inst/u_spi_arbiter/n73_s2 .INIT=16'h0007; LUT4 \spiflash_inst/u_spi_arbiter/n101_s1 ( .I0(\spiflash_inst/u_spi_arbiter/n75_7 ), .I1(\spiflash_inst/arb_cs_r [1]), .I2(\spiflash_inst/u_spi_arbiter/n74_8 ), .I3(\spiflash_inst/n74_7 ), .F(\spiflash_inst/u_spi_arbiter/n101_5 ) ); defparam \spiflash_inst/u_spi_arbiter/n101_s1 .INIT=16'h4100; LUT4 \spiflash_inst/u_spi_arbiter/n75_s3 ( .I0(\spiflash_inst/u_spi_arbiter/n75_14 ), .I1(\spiflash_inst/arb_cs_r [1]), .I2(\spiflash_inst/arb_cs_r [2]), .I3(\spiflash_inst/u_spi_arbiter/n75_9 ), .F(\spiflash_inst/u_spi_arbiter/n75_7 ) ); defparam \spiflash_inst/u_spi_arbiter/n75_s3 .INIT=16'h00BF; LUT2 \spiflash_inst/u_spi_arbiter/n74_s3 ( .I0(\spiflash_inst/reg_req_r ), .I1(\spiflash_inst/n220_9 ), .F(\spiflash_inst/n74_7 ) ); defparam \spiflash_inst/u_spi_arbiter/n74_s3 .INIT=4'h8; LUT2 \spiflash_inst/u_spi_arbiter/n74_s4 ( .I0(\spiflash_inst/u_spi_arbiter/n74_9 ), .I1(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/u_spi_arbiter/n74_8 ) ); defparam \spiflash_inst/u_spi_arbiter/n74_s4 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_arbiter/n73_s4 ( .I0(\spiflash_inst/u_spi_arbiter/arb_cs_r_0 [0]), .I1(\spiflash_inst/arb_busy_sysclk ), .I2(\spiflash_inst/arb_cs_r [1]), .I3(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/u_spi_arbiter/n73_8 ) ); defparam \spiflash_inst/u_spi_arbiter/n73_s4 .INIT=16'h00EF; LUT4 \spiflash_inst/u_spi_arbiter/n75_s5 ( .I0(\spiflash_inst/arb_busy_sysclk ), .I1(\spiflash_inst/n74_7 ), .I2(\spiflash_inst/u_spi_arbiter/arb_cs_r_0 [0]), .I3(\spiflash_inst/u_spi_arbiter/n75_12 ), .F(\spiflash_inst/u_spi_arbiter/n75_9 ) ); defparam \spiflash_inst/u_spi_arbiter/n75_s5 .INIT=16'hF400; LUT4 \spiflash_inst/u_spi_arbiter/n74_s5 ( .I0(\spiflash_inst/rxf_clr_level_Z ), .I1(\spiflash_inst/arb_busy_sysclk ), .I2(\spiflash_inst/u_spi_arbiter/arb_cs_r_0 [0]), .I3(\spiflash_inst/arb_cs_r [1]), .F(\spiflash_inst/u_spi_arbiter/n74_9 ) ); defparam \spiflash_inst/u_spi_arbiter/n74_s5 .INIT=16'hCAFC; LUT3 \spiflash_inst/u_spi_arbiter/n73_s5 ( .I0(\spiflash_inst/arb_cs_r [1]), .I1(\spiflash_inst/u_spi_arbiter/n74_9 ), .I2(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/u_spi_arbiter/n73_10 ) ); defparam \spiflash_inst/u_spi_arbiter/n73_s5 .INIT=8'h20; LUT3 \spiflash_inst/u_spi_arbiter/n75_s7 ( .I0(\spiflash_inst/spi_trans_end_int_r_15 ), .I1(\spiflash_inst/arb_cs_r [1]), .I2(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/u_spi_arbiter/n75_12 ) ); defparam \spiflash_inst/u_spi_arbiter/n75_s7 .INIT=8'h01; LUT3 \spiflash_inst/u_spi_arbiter/arb_rxf_clr_Z_s0 ( .I0(I_pwdata[1]), .I1(\spiflash_inst/reg_spi_format_wr_4 ), .I2(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/arb_rxf_clr_Z ) ); defparam \spiflash_inst/u_spi_arbiter/arb_rxf_clr_Z_s0 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_arbiter/n75_s8 ( .I0(\spiflash_inst/reg_req_r ), .I1(\spiflash_inst/n220_9 ), .I2(\spiflash_inst/rxf_clr_level_Z ), .I3(\spiflash_inst/u_spi_arbiter/arb_cs_r_0 [0]), .F(\spiflash_inst/u_spi_arbiter/n75_14 ) ); defparam \spiflash_inst/u_spi_arbiter/n75_s8 .INIT=16'h00F7; DFFCE \spiflash_inst/u_spi_arbiter/arb_cs_r_1_s0 ( .D(\spiflash_inst/u_spi_arbiter/n74_6 ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_cs_r [1]) ); defparam \spiflash_inst/u_spi_arbiter/arb_cs_r_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_arbiter/arb_cs_r_0_s0 ( .D(\spiflash_inst/u_spi_arbiter/n75_6 ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_arbiter/arb_cs_r_0 [0]) ); defparam \spiflash_inst/u_spi_arbiter/arb_cs_r_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_arbiter/arb_req_sysclk_s0 ( .D(\spiflash_inst/u_spi_arbiter/n101_5 ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_req_sysclk_Z ) ); defparam \spiflash_inst/u_spi_arbiter/arb_req_sysclk_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_arbiter/arb_cs_r_2_s0 ( .D(\spiflash_inst/u_spi_arbiter/n73_6 ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_cs_r [2]) ); defparam \spiflash_inst/u_spi_arbiter/arb_cs_r_2_s0 .INIT=1'b0; LUT2 \spiflash_inst/u_spi_fifo/n19_s1 ( .I0(\spiflash_inst/txf_clr_level_Z ), .I1(I_presetn), .F(\spiflash_inst/u_spi_fifo/n19_4 ) ); defparam \spiflash_inst/u_spi_fifo/n19_s1 .INIT=4'hB; LUT2 \spiflash_inst/u_spi_fifo/n21_s1 ( .I0(\spiflash_inst/u_spi_fifo/txf_clr_sclk ), .I1(I_spi_rstn), .F(\spiflash_inst/u_spi_fifo/n21_4 ) ); defparam \spiflash_inst/u_spi_fifo/n21_s1 .INIT=4'hB; LUT2 \spiflash_inst/u_spi_fifo/n83_s1 ( .I0(\spiflash_inst/u_spi_fifo/rxf_clr_sclk ), .I1(I_spi_rstn), .F(\spiflash_inst/u_spi_fifo/n83_4 ) ); defparam \spiflash_inst/u_spi_fifo/n83_s1 .INIT=4'hB; LUT2 \spiflash_inst/u_spi_fifo/n85_s1 ( .I0(\spiflash_inst/rxf_clr_level_Z ), .I1(I_presetn), .F(\spiflash_inst/u_spi_fifo/n85_4 ) ); defparam \spiflash_inst/u_spi_fifo/n85_s1 .INIT=4'hB; LUT4 \spiflash_inst/u_spi_fifo/txf_clr_level_s4 ( .I0(\spiflash_inst/u_spi_fifo/txf_clr_ack ), .I1(I_pwdata[2]), .I2(\spiflash_inst/reg_spi_format_wr_4 ), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_fifo/txf_clr_level_7 ) ); defparam \spiflash_inst/u_spi_fifo/txf_clr_level_s4 .INIT=16'hEAAA; LUT4 \spiflash_inst/u_spi_fifo/rxf_clr_level_s4 ( .I0(\spiflash_inst/u_spi_fifo/rxf_clr_ack ), .I1(I_pwdata[1]), .I2(\spiflash_inst/reg_spi_format_wr_4 ), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_fifo/rxf_clr_level_7 ) ); defparam \spiflash_inst/u_spi_fifo/rxf_clr_level_s4 .INIT=16'hEAAA; DFFPE \spiflash_inst/u_spi_fifo/rxf_empty_d2_s0 ( .D(\spiflash_inst/u_spi_fifo/rxf_empty_d1 ), .CLK(I_pclk), .CE(VCC), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/rxf_empty ) ); defparam \spiflash_inst/u_spi_fifo/rxf_empty_d2_s0 .INIT=1'b1; DFFPE \spiflash_inst/u_spi_fifo/rxf_empty_d1_s0 ( .D(\spiflash_inst/u_spi_fifo/rxf_empty_tmp ), .CLK(I_pclk), .CE(VCC), .PRESET(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_fifo/rxf_empty_d1 ) ); defparam \spiflash_inst/u_spi_fifo/rxf_empty_d1_s0 .INIT=1'b1; DFFCE \spiflash_inst/u_spi_fifo/rxf_clr_level_s1 ( .D(\spiflash_inst/arb_rxf_clr_Z ), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_fifo/rxf_clr_level_7 ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/rxf_clr_level_Z ) ); defparam \spiflash_inst/u_spi_fifo/rxf_clr_level_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/txf_clr_level_s1 ( .D(\spiflash_inst/reg_txf_clr_regclk_Z ), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_fifo/txf_clr_level_7 ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/txf_clr_level_Z ) ); defparam \spiflash_inst/u_spi_fifo/txf_clr_level_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/txf_clr_sync/b_signal_s0 ( .D(\spiflash_inst/u_spi_fifo/txf_clr_sync/a_signal_sync1 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_fifo/txf_clr_sclk ) ); defparam \spiflash_inst/u_spi_fifo/txf_clr_sync/b_signal_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/txf_clr_sync/a_signal_sync1_s0 ( .D(\spiflash_inst/txf_clr_level_Z ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_fifo/txf_clr_sync/a_signal_sync1 ) ); defparam \spiflash_inst/u_spi_fifo/txf_clr_sync/a_signal_sync1_s0 .INIT=1'b0; INV \spiflash_inst/u_spi_fifo/txf_clr_sync/n6_s2 ( .I(I_spi_rstn), .O(\spiflash_inst/n6_6 ) ); DFFCE \spiflash_inst/u_spi_fifo/txf_clr_ack_sync/b_signal_s0 ( .D(\spiflash_inst/u_spi_fifo/txf_clr_ack_sync/a_signal_sync1 ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_fifo/txf_clr_ack ) ); defparam \spiflash_inst/u_spi_fifo/txf_clr_ack_sync/b_signal_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/txf_clr_ack_sync/a_signal_sync1_s0 ( .D(\spiflash_inst/u_spi_fifo/txf_clr_sclk ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_fifo/txf_clr_ack_sync/a_signal_sync1 ) ); defparam \spiflash_inst/u_spi_fifo/txf_clr_ack_sync/a_signal_sync1_s0 .INIT=1'b0; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_4_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [4]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_4_6 ), .I3(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_4_s2 .INIT=16'h3CAA; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_3_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [3]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_3_8 ), .I3(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_3_s2 .INIT=16'h3CAA; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_2_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [2]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_2_6 ), .I3(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_2_s2 .INIT=16'h3CAA; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_1_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [0]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [1]), .I3(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_1_s2 .INIT=16'h3CAA; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_0_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_0_8 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly [0]), .I2(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_0_s2 .INIT=8'h5C; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_0_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [0]), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_0_s0 .INIT=8'h1E; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_0_8 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_4 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [1]), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [2]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_s0 .INIT=16'h07F8; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_4 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [3]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_s0 .INIT=8'h1E; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_3_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_4 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [3]), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_3_s0 .INIT=16'h07F8; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_4_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_4 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_4_6 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [4]), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_4_s0 .INIT=16'h07F8; LUT2 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_2_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_2_4 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_2_s0 .INIT=4'h9; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_4 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_5 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_6 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_s0 .INIT=8'h40; LUT2 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w_4_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [5]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w_4_s0 .INIT=4'h6; LUT2 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w_1_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [2]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w_1_s0 .INIT=4'h6; LUT2 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w_0_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [0]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w_0_s0 .INIT=4'h6; LUT2 \spiflash_inst/u_spi_fifo/u_spi_txfifo/n245_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [5]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n245_3 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/n245_s0 .INIT=4'h6; LUT2 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_0_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [0]), .I1(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_0_7 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_0_s3 .INIT=4'h6; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_1_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_0_8 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_4 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_1_s3 .INIT=8'h78; LUT2 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_2_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_4 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_2_s3 .INIT=4'h6; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_3_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_4 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [3]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_3_s3 .INIT=8'h78; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_4_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_4 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_4_6 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_4_s3 .INIT=8'h78; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_5_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_4 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_4_6 ), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_5_s2 .INIT=16'h7F80; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_1_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [0]), .I1(\spiflash_inst/reg_txf_wr_regclk_Z ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_1_s3 .INIT=8'h78; LUT2 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_2_4 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_8 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_s3 .INIT=4'h1; LUT2 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_3_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_8 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_3_s3 .INIT=4'h6; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_4_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_8 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_4_s3 .INIT=8'h78; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_5_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [4]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_8 ), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_5_s2 .INIT=16'h7F80; LUT2 \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_4_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_3_8 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_4_6 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_4_s3 .INIT=4'h8; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_2_s3 ( .I0(\spiflash_inst/txf_empty ), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [0]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_2_6 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_2_s3 .INIT=8'h40; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_s1 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/n243_21 ), .I2(\spiflash_inst/n245_21 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_4 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_1_s1 .INIT=8'h14; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_s1 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/n243_21 ), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_5 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_4 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_s1 .INIT=16'h1400; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_2_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [0]), .I2(\spiflash_inst/reg_txf_wr_regclk_Z ), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [2]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_2_4 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_2_s1 .INIT=16'h007F; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [5]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [4]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [4]), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_4 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_s1 .INIT=16'hBED7; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [0]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [0]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [1]), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_5 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_s2 .INIT=16'h9009; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [2]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [3]), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [3]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_6 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val_s3 .INIT=16'h9009; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_s4 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [0]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [1]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [2]), .I3(\spiflash_inst/reg_txf_wr_regclk_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_8 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_s4 .INIT=16'h8000; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_s2 ( .I0(\spiflash_inst/n242_24 ), .I1(\spiflash_inst/n242_23 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_2_6 ), .I3(\spiflash_inst/txf_rd_Z_4 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_5 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_2_s2 .INIT=16'hE000; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w_3_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [5]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w_3_s1 .INIT=8'h96; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_1_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_2_4 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_8 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_1_s1 .INIT=8'hA9; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_3_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_8 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_3_s1 .INIT=8'h96; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_4_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_4_6 ), .I1(\spiflash_inst/n242_24 ), .I2(\spiflash_inst/n242_23 ), .I3(\spiflash_inst/txf_rd_Z_4 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_4_6 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_4_s2 .INIT=16'hA800; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_0_s4 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [0]), .I1(\spiflash_inst/n242_24 ), .I2(\spiflash_inst/n242_23 ), .I3(\spiflash_inst/txf_rd_Z_4 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_0_8 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_0_s4 .INIT=16'hA800; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_3_s4 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [2]), .I1(\spiflash_inst/txf_empty ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [0]), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_3_8 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f_3_s4 .INIT=16'h2000; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_0_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_0_9 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [0]), .I2(\spiflash_inst/reg_txf_wr_regclk_Z ), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_0_s1 .INIT=16'h956A; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_4_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_2_8 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [4]), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext_4_s1 .INIT=16'h8778; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_0_s4 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [0]), .I1(\spiflash_inst/reg_txf_full ), .I2(\spiflash_inst/reg_rd_a_Z_4 ), .I3(\spiflash_inst/reg_spi_format_wr_4 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_0_9 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_0_s4 .INIT=16'h9AAA; LUT3 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [5]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [5]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n188_3 ), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val_s1 .INIT=8'h09; LUT4 \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w_2_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [3]), .I2(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [5]), .I3(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w_2_s1 .INIT=16'h6996; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [3]), .CLK(I_spi_clock), .CE(\spiflash_inst/txf_rd_Z ), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [2]), .CLK(I_spi_clock), .CE(\spiflash_inst/txf_rd_Z ), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [1]), .CLK(I_spi_clock), .CE(\spiflash_inst/txf_rd_Z ), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_0_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/txf_rd_Z ), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [5]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [4]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [3]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [2]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [1]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next_0_7 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num [5]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr [4]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr [3]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr [2]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr [1]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr [0]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [5]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [4]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [3]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [2]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [1]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr [0]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [5]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [4]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [3]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [2]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [1]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [0]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [5]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [4]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [3]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [2]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [1]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq1_wptr [0]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [4]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [3]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [2]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [1]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [0]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/rptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [5]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [4]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [3]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [2]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [1]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wgraynext [0]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [4]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [3]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [2]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext [1]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbinnext_0_9 ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/Full_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wfull_val ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/reg_txf_full ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/Full_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [5]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/reg_txf_entries [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [4]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/reg_txf_entries [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [3]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/reg_txf_entries [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [2]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/reg_txf_entries [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [1]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/reg_txf_entries [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [0]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n19_4 ), .Q(\spiflash_inst/reg_txf_entries [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/Wnum_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rbin_num_next [4]), .CLK(I_spi_clock), .CE(\spiflash_inst/txf_rd_Z ), .CLEAR(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_dly_4_s0 .INIT=1'b0; DFFPE \spiflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val ), .CLK(I_spi_clock), .CE(VCC), .PRESET(\spiflash_inst/u_spi_fifo/n21_4 ), .Q(\spiflash_inst/txf_empty ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0 .INIT=1'b1; SDPB \spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s ( .CLKA(I_pclk), .CEA(\spiflash_inst/reg_txf_wr_regclk_Z ), .CLKB(I_spi_clock), .CEB(\spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_7 ), .OCE(GND), .RESET(\spiflash_inst/u_spi_fifo/n21_4 ), .BLKSELA({GND, GND, GND}), .BLKSELB({GND, GND, GND}), .DI({I_pwdata[31:0]}), .ADA({GND, GND, GND, GND, \spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [4:0], GND, VCC, VCC, VCC, VCC}), .ADB({GND, GND, GND, GND, \spiflash_inst/u_spi_fifo/u_spi_txfifo/raddr_num_f [4:0], GND, GND, GND, GND, GND}), .DO({\spiflash_inst/txf_rd_data [31:0]}) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s .READ_MODE=1'b0; defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s .BIT_WIDTH_0=32; defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s .BIT_WIDTH_1=32; defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s .RESET_MODE="ASYNC"; defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s .BLK_SEL_0=3'b000; defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s .BLK_SEL_1=3'b000; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_0_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [0]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [0]), .I3(GND), .CIN(VCC), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_0_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_0_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_1_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_0_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_1_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_1_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_2_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_1_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_2_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_2_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_3_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [3]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_2_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_3_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_3_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_4_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wbin [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rcount_w [4]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_3_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_4_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_4_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_5_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n245_3 ), .I1(GND), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_4_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_5_0_COUT ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/wcnt_sub_5_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/n184_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [0]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [0]), .I3(GND), .CIN(GND), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n184_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n184_1_SUM ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/n184_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/n185_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n184_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n185_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n185_1_SUM ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/n185_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/n186_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n185_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n186_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n186_1_SUM ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/n186_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/n187_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [3]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n186_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n187_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n187_1_SUM ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/n187_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_fifo/u_spi_txfifo/n188_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_txfifo/rq2_wptr [4]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n187_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n188_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_txfifo/n188_1_SUM ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_txfifo/n188_s0 .ALU_MODE=3; INV \spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_s5 ( .I(\spiflash_inst/txf_empty ), .O(\spiflash_inst/u_spi_fifo/u_spi_txfifo/mem_7 ) ); DFFCE \spiflash_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0 ( .D(\spiflash_inst/u_spi_fifo/rxf_clr_sync/a_signal_sync1 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_fifo/rxf_clr_sclk ) ); defparam \spiflash_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/rxf_clr_sync/a_signal_sync1_s0 ( .D(\spiflash_inst/rxf_clr_level_Z ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_fifo/rxf_clr_sync/a_signal_sync1 ) ); defparam \spiflash_inst/u_spi_fifo/rxf_clr_sync/a_signal_sync1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/rxf_clr_ack_sync/b_signal_s0 ( .D(\spiflash_inst/u_spi_fifo/rxf_clr_ack_sync/a_signal_sync1 ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_fifo/rxf_clr_ack ) ); defparam \spiflash_inst/u_spi_fifo/rxf_clr_ack_sync/b_signal_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/rxf_clr_ack_sync/a_signal_sync1_s0 ( .D(\spiflash_inst/u_spi_fifo/rxf_clr_sclk ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_fifo/rxf_clr_ack_sync/a_signal_sync1 ) ); defparam \spiflash_inst/u_spi_fifo/rxf_clr_ack_sync/a_signal_sync1_s0 .INIT=1'b0; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f_4_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly [4]), .I2(\spiflash_inst/reg_rxf_rd_regclk_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f_4_s2 .INIT=8'hAC; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f_3_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly [3]), .I2(\spiflash_inst/reg_rxf_rd_regclk_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f_3_s2 .INIT=8'hAC; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f_1_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly [1]), .I2(\spiflash_inst/reg_rxf_rd_regclk_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f_1_s2 .INIT=8'hAC; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f_0_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_0_7 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly [0]), .I2(\spiflash_inst/reg_rxf_rd_regclk_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f_0_s2 .INIT=8'hAC; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext_4_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext_4_s0 .INIT=4'h6; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r_4_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [5]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r_4_s0 .INIT=4'h6; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r_1_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [2]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r_1_s0 .INIT=4'h6; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r_0_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [0]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r_0_s0 .INIT=4'h6; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n197_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [5]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n197_3 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n197_s0 .INIT=4'h6; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext_3_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext_3_s0 .INIT=4'h6; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext_4_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext_4_s0 .INIT=4'h6; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_4 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_5 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_6 ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_s0 .INIT=8'h40; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_0_s3 ( .I0(\spiflash_inst/u_spi_fifo/rxf_empty_tmp ), .I1(\spiflash_inst/reg_rxf_rd_regclk_Z ), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [0]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_0_7 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_0_s3 .INIT=8'hB4; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_1_s3 ( .I0(\spiflash_inst/u_spi_fifo/rxf_empty_tmp ), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [0]), .I2(\spiflash_inst/reg_rxf_rd_regclk_Z ), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_1_s3 .INIT=16'hBF40; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_8 ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_s3 .INIT=4'h6; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_3_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_8 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [3]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_3_s3 .INIT=8'h78; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_5_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_8 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_4_8 ), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_5_s2 .INIT=16'h7F80; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_10 ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_s3 .INIT=4'h6; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_5_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [4]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_3_8 ), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_5_s2 .INIT=16'h7F80; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [5]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [4]), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [5]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_4 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_s1 .INIT=16'hDEB7; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_s2 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [0]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [0]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [1]), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_5 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_s2 .INIT=16'h9009; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [2]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [3]), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [3]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_6 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val_s3 .INIT=16'h9009; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_s4 ( .I0(\spiflash_inst/u_spi_fifo/rxf_empty_tmp ), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [0]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [1]), .I3(\spiflash_inst/reg_rxf_rd_regclk_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_8 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_s4 .INIT=16'h4000; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_4_s4 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [3]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_4_8 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_4_s4 .INIT=4'h8; LUT2 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_3_s4 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_10 ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_3_8 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_3_s4 .INIT=4'h8; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_4_s5 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_8 ), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [2]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [3]), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_4_s5 .INIT=16'h7F80; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r_3_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [5]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r_3_s1 .INIT=8'h96; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext_0_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [1]), .I1(\spiflash_inst/u_spi_fifo/rxf_empty_tmp ), .I2(\spiflash_inst/reg_rxf_rd_regclk_Z ), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [0]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext_0_s1 .INIT=16'h659A; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext_2_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [2]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_8 ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext_2_s1 .INIT=8'h96; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext_1_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_8 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext_1_s1 .INIT=8'h96; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f_2_s3 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_8 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly [2]), .I3(\spiflash_inst/reg_rxf_rd_regclk_Z ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f_2_s3 .INIT=16'h66F0; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext_3_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [2]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_2_8 ), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [3]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext_3_s1 .INIT=16'h956A; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_s5 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [0]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [1]), .I2(\spiflash_inst/rxf_full ), .I3(\spiflash_inst/rx_shift_reg_full_r ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_10 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_s5 .INIT=16'h0800; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_1_s4 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [0]), .I1(\spiflash_inst/rxf_full ), .I2(\spiflash_inst/rx_shift_reg_full_r ), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_1_s4 .INIT=16'hDF20; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_0_s4 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [0]), .I1(\spiflash_inst/rxf_full ), .I2(\spiflash_inst/rx_shift_reg_full_r ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_0_9 ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_0_s4 .INIT=8'h9A; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rempty_val_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [5]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [5]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n188_3 ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rempty_val ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rempty_val_s1 .INIT=8'h09; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext_0_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [0]), .I1(\spiflash_inst/rxf_full ), .I2(\spiflash_inst/rx_shift_reg_full_r ), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [1]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext_0_s1 .INIT=16'h659A; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r_2_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [3]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [5]), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r_2_s1 .INIT=16'h6996; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext_2_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_10 ), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [3]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext_2_s1 .INIT=8'h96; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext_1_s1 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [2]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_10 ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext_1_s1 .INIT=8'h96; LUT4 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_4_s4 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [2]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_10 ), .I3(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [4]), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_4_s4 .INIT=16'h7F80; LUT3 \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_3_s5 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [2]), .I2(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_2_10 ), .F(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_3_s5 .INIT=8'h6A; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [3]), .CLK(I_pclk), .CE(\spiflash_inst/reg_rxf_rd_regclk_Z ), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [2]), .CLK(I_pclk), .CE(\spiflash_inst/reg_rxf_rd_regclk_Z ), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [1]), .CLK(I_pclk), .CE(\spiflash_inst/reg_rxf_rd_regclk_Z ), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_0_7 ), .CLK(I_pclk), .CE(\spiflash_inst/reg_rxf_rd_regclk_Z ), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [5]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [4]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [3]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [2]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [1]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next_0_7 ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [5]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr [4]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr [3]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr [2]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr [1]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr [0]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [5]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [4]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [3]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [2]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [1]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr [0]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [5]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [4]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [3]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [2]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [1]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [0]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [5]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [4]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [3]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [2]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [1]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq1_wptr [0]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [4]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [3]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [2]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [1]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [0]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [5]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [4]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [3]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [2]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [1]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wgraynext [0]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wptr_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [4]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [3]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [2]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext [1]), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbinnext_0_9 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Full_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wfull_val ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n83_4 ), .Q(\spiflash_inst/rxf_full ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Full_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_5_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [5]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/rxf_entries [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_5_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [4]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/rxf_entries [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_4_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_3_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [3]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/rxf_entries [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_2_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [2]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/rxf_entries [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_1_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [1]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/rxf_entries [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_0_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [0]), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/rxf_entries [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Rnum_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly_4_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num_next [4]), .CLK(I_pclk), .CE(\spiflash_inst/reg_rxf_rd_regclk_Z ), .CLEAR(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_dly_4_s0 .INIT=1'b0; DFFPE \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Empty_s0 ( .D(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rempty_val ), .CLK(I_pclk), .CE(VCC), .PRESET(\spiflash_inst/u_spi_fifo/n85_4 ), .Q(\spiflash_inst/u_spi_fifo/rxf_empty_tmp ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/Empty_s0 .INIT=1'b1; SDPB \spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_mem_0_0_s ( .CLKA(I_spi_clock), .CEA(\spiflash_inst/rxf_wr_Z ), .CLKB(I_pclk), .CEB(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_7 ), .OCE(GND), .RESET(\spiflash_inst/u_spi_fifo/n85_4 ), .BLKSELA({GND, GND, GND}), .BLKSELB({GND, GND, GND}), .DI({\spiflash_inst/rxf_wr_data_Z [31:0]}), .ADA({GND, GND, GND, GND, \spiflash_inst/u_spi_fifo/u_spi_rxfifo/wbin [4:0], GND, VCC, VCC, VCC, VCC}), .ADB({GND, GND, GND, GND, \spiflash_inst/u_spi_fifo/u_spi_rxfifo/raddr_num_f [4:0], GND, GND, GND, GND, GND}), .DO({\spiflash_inst/rxf_rd_data [31:0]}) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_mem_0_0_s .READ_MODE=1'b0; defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_mem_0_0_s .BIT_WIDTH_0=32; defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_mem_0_0_s .BIT_WIDTH_1=32; defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_mem_0_0_s .RESET_MODE="ASYNC"; defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_mem_0_0_s .BLK_SEL_0=3'b000; defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_mem_0_0_s .BLK_SEL_1=3'b000; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_0_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [0]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [0]), .I3(GND), .CIN(VCC), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_0_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [0]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_0_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_1_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_0_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_1_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [1]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_1_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_2_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_1_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_2_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [2]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_2_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_3_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [3]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_2_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_3_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [3]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_3_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_4_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/wcount_r [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rbin_num [4]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_3_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_4_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [4]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_4_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_5_s ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n197_3 ), .I1(GND), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_4_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_5_0_COUT ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub [5]) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/rcnt_sub_5_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n184_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [0]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [0]), .I3(GND), .CIN(GND), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n184_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n184_1_SUM ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n184_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n185_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [1]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n184_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n185_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n185_1_SUM ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n185_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n186_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [2]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n185_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n186_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n186_1_SUM ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n186_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n187_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [3]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [3]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n186_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n187_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n187_1_SUM ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n187_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n188_s0 ( .I0(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rgraynext [4]), .I1(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/rq2_wptr [4]), .I3(GND), .CIN(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n187_3 ), .COUT(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n188_3 ), .SUM(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/n188_1_SUM ) ); defparam \spiflash_inst/u_spi_fifo/u_spi_rxfifo/n188_s0 .ALU_MODE=3; INV \spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_s5 ( .I(\spiflash_inst/u_spi_fifo/rxf_empty_tmp ), .O(\spiflash_inst/u_spi_fifo/u_spi_rxfifo/mem_7 ) ); LUT4 \spiflash_inst/u_spi_sync/spi_reset_sysclk_s4 ( .I0(\spiflash_inst/u_spi_sync/spi_reset_ack ), .I1(I_pwdata[0]), .I2(\spiflash_inst/reg_spi_format_wr_4 ), .I3(\spiflash_inst/reg_reg_ctrl_wr_7 ), .F(\spiflash_inst/u_spi_sync/spi_reset_sysclk_7 ) ); defparam \spiflash_inst/u_spi_sync/spi_reset_sysclk_s4 .INIT=16'hEAAA; DFFCE \spiflash_inst/u_spi_sync/spi_reset_sysclk_s1 ( .D(\spiflash_inst/spi_reset_regclk_Z ), .CLK(I_pclk), .CE(\spiflash_inst/u_spi_sync/spi_reset_sysclk_7 ), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/spi_reset_sysclk_Z ) ); defparam \spiflash_inst/u_spi_sync/spi_reset_sysclk_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/arb_req_sync/b_signal_s0 ( .D(\spiflash_inst/u_spi_sync/arb_req_sync/a_signal_sync1 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/arb_req_sclk ) ); defparam \spiflash_inst/u_spi_sync/arb_req_sync/b_signal_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/arb_req_sync/a_signal_sync1_s0 ( .D(\spiflash_inst/arb_req_sysclk_Z ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_sync/arb_req_sync/a_signal_sync1 ) ); defparam \spiflash_inst/u_spi_sync/arb_req_sync/a_signal_sync1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/arb_busy_sync/b_signal_s0 ( .D(\spiflash_inst/u_spi_sync/arb_busy_sync/a_signal_sync1 ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/arb_busy_sysclk ) ); defparam \spiflash_inst/u_spi_sync/arb_busy_sync/b_signal_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/arb_busy_sync/a_signal_sync1_s0 ( .D(\spiflash_inst/arb_busy_sclk_Z ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_sync/arb_busy_sync/a_signal_sync1 ) ); defparam \spiflash_inst/u_spi_sync/arb_busy_sync/a_signal_sync1_s0 .INIT=1'b0; LUT3 \spiflash_inst/u_spi_sync/arb_trans_end_sync/n8_s3 ( .I0(\spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_r ), .I1(\spiflash_inst/arb_trans_end_sclk_Z_3 ), .I2(\spiflash_inst/arb_trans_end_sclk_Z_4 ), .F(\spiflash_inst/u_spi_sync/arb_trans_end_sync/n8_10 ) ); defparam \spiflash_inst/u_spi_sync/arb_trans_end_sync/n8_s3 .INIT=8'h9A; DFFCE \spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_sync2b_syn1_r_s0 ( .D(\spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_r ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_sync2b_syn1_r ) ); defparam \spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_sync2b_syn1_r_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_sync2b_syn2_r_s0 ( .D(\spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_sync2b_syn1_r ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/a_level_sync2b_syn2_r ) ); defparam \spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_sync2b_syn2_r_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_sync2b_syn3_r_s0 ( .D(\spiflash_inst/a_level_sync2b_syn2_r ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/a_level_sync2b_syn3_r ) ); defparam \spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_sync2b_syn3_r_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_r_s2 ( .D(\spiflash_inst/u_spi_sync/arb_trans_end_sync/n8_10 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_r ) ); defparam \spiflash_inst/u_spi_sync/arb_trans_end_sync/a_level_r_s2 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/spi_reset_sync/b_signal_s0 ( .D(\spiflash_inst/u_spi_sync/spi_reset_sync/a_signal_sync1 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/spi_reset_sclk ) ); defparam \spiflash_inst/u_spi_sync/spi_reset_sync/b_signal_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/spi_reset_sync/a_signal_sync1_s0 ( .D(\spiflash_inst/spi_reset_sysclk_Z ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_sync/spi_reset_sync/a_signal_sync1 ) ); defparam \spiflash_inst/u_spi_sync/spi_reset_sync/a_signal_sync1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/spi_reset_ack_sync/b_signal_s0 ( .D(\spiflash_inst/u_spi_sync/spi_reset_ack_sync/a_signal_sync1 ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_sync/spi_reset_ack ) ); defparam \spiflash_inst/u_spi_sync/spi_reset_ack_sync/b_signal_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_sync/spi_reset_ack_sync/a_signal_sync1_s0 ( .D(\spiflash_inst/spi_reset_sclk ), .CLK(I_pclk), .CE(VCC), .CLEAR(\spiflash_inst/n11_6 ), .Q(\spiflash_inst/u_spi_sync/spi_reset_ack_sync/a_signal_sync1 ) ); defparam \spiflash_inst/u_spi_sync/spi_reset_ack_sync/a_signal_sync1_s0 .INIT=1'b0; LUT3 \spiflash_inst/u_spi_ctrl/n1018_s16 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [0]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [4]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1018_10 ) ); defparam \spiflash_inst/u_spi_ctrl/n1018_s16 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1018_s17 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [8]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [12]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1018_11 ) ); defparam \spiflash_inst/u_spi_ctrl/n1018_s17 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1018_s18 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [16]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [20]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1018_12 ) ); defparam \spiflash_inst/u_spi_ctrl/n1018_s18 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1018_s19 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [24]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [28]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1018_13 ) ); defparam \spiflash_inst/u_spi_ctrl/n1018_s19 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1022_s16 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [1]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [5]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1022_10 ) ); defparam \spiflash_inst/u_spi_ctrl/n1022_s16 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1022_s17 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [9]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [13]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1022_11 ) ); defparam \spiflash_inst/u_spi_ctrl/n1022_s17 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1022_s18 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [17]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [21]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1022_12 ) ); defparam \spiflash_inst/u_spi_ctrl/n1022_s18 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1022_s19 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [25]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [29]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1022_13 ) ); defparam \spiflash_inst/u_spi_ctrl/n1022_s19 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1026_s16 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [2]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [6]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1026_10 ) ); defparam \spiflash_inst/u_spi_ctrl/n1026_s16 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1026_s17 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [10]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [14]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1026_11 ) ); defparam \spiflash_inst/u_spi_ctrl/n1026_s17 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1026_s18 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [18]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [22]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1026_12 ) ); defparam \spiflash_inst/u_spi_ctrl/n1026_s18 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1026_s19 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [26]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [30]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1026_13 ) ); defparam \spiflash_inst/u_spi_ctrl/n1026_s19 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1030_s16 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [3]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [7]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1030_10 ) ); defparam \spiflash_inst/u_spi_ctrl/n1030_s16 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1030_s17 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [11]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [15]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1030_11 ) ); defparam \spiflash_inst/u_spi_ctrl/n1030_s17 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1030_s18 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [19]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [23]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1030_12 ) ); defparam \spiflash_inst/u_spi_ctrl/n1030_s18 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1030_s19 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [27]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [31]), .I2(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/n1030_13 ) ); defparam \spiflash_inst/u_spi_ctrl/n1030_s19 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s108 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [0]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [1]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_68 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s108 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s109 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [2]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [3]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_69 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s109 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s110 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [4]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [5]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_70 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s110 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s111 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [6]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [7]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_71 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s111 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s112 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [8]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [9]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_72 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s112 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s113 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [10]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [11]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_73 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s113 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s114 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [12]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [13]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_74 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s114 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s115 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [14]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [15]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_75 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s115 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s116 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [16]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [17]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_76 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s116 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s117 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [18]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [19]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_77 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s117 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s118 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [20]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [21]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_78 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s118 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s119 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [22]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [23]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_79 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s119 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s120 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [24]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [25]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_80 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s120 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s121 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [26]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [27]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_81 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s121 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s122 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [28]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [29]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_82 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s122 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s123 ( .I0(\spiflash_inst/u_spi_ctrl/tx_mux_r [30]), .I1(\spiflash_inst/u_spi_ctrl/tx_mux_r [31]), .I2(\spiflash_inst/u_spi_ctrl/tx_ptr [0]), .F(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_83 ) ); defparam \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s123 .INIT=8'hCA; LUT4 \spiflash_inst/u_spi_ctrl/txf_rd_Z_s ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/n243_21 ), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/txf_rd_Z_3 ), .F(\spiflash_inst/txf_rd_Z ) ); defparam \spiflash_inst/u_spi_ctrl/txf_rd_Z_s .INIT=16'h1400; LUT4 \spiflash_inst/u_spi_ctrl/n852_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n852_11 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [31]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n852_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n852_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n853_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n853_8 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n853_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n853_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n853_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n854_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n854_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n854_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n854_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n854_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n855_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n855_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [28]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n855_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n855_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n856_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n856_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n856_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n856_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n856_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n857_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n857_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [26]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n857_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n857_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n858_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n858_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [25]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n858_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n858_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n859_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n859_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n859_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n859_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n859_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n860_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n860_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [23]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n860_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n860_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n861_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n861_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n861_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n861_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n861_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n862_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n862_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n862_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n862_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n862_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n863_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n863_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [20]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n863_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n863_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n864_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n864_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n864_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n864_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n864_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n865_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n865_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [18]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n865_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n865_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n866_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n866_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [17]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n866_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n866_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n867_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n867_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n867_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n867_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n867_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n868_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n868_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [15]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n868_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n868_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n869_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n869_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n869_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n869_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n869_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n870_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n870_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n870_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n870_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n870_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n871_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n871_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [12]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n871_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n871_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n872_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n872_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n872_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n872_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n872_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n873_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n873_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [10]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n873_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n873_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n874_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n874_6 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/arb_addr [9]), .I3(\spiflash_inst/u_spi_ctrl/n852_5 ), .F(\spiflash_inst/u_spi_ctrl/n874_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n874_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n875_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n875_7 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n875_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n875_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n875_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n876_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n876_4 ), .I1(\spiflash_inst/u_spi_ctrl/n876_10 ), .I2(\spiflash_inst/u_spi_ctrl/n876_8 ), .I3(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_ctrl/n876_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n876_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n877_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n877_8 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n877_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n877_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n877_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n878_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n878_8 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n878_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n878_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n878_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n879_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n879_4 ), .I1(\spiflash_inst/u_spi_ctrl/n876_10 ), .I2(\spiflash_inst/u_spi_ctrl/n879_7 ), .I3(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_ctrl/n879_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n879_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n880_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n880_8 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n880_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n880_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n880_s0 .INIT=16'hFFF8; LUT4 \spiflash_inst/u_spi_ctrl/n881_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n881_4 ), .I1(\spiflash_inst/u_spi_ctrl/n876_10 ), .I2(\spiflash_inst/u_spi_ctrl/n881_7 ), .I3(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_ctrl/n881_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n881_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n882_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n882_4 ), .I1(\spiflash_inst/u_spi_ctrl/n876_10 ), .I2(\spiflash_inst/u_spi_ctrl/n882_7 ), .I3(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_ctrl/n882_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n882_s0 .INIT=16'hF888; LUT4 \spiflash_inst/u_spi_ctrl/n883_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n883_8 ), .I1(\spiflash_inst/txf_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n883_5 ), .I3(\spiflash_inst/u_spi_ctrl/n853_6 ), .F(\spiflash_inst/u_spi_ctrl/n883_3 ) ); defparam \spiflash_inst/u_spi_ctrl/n883_s0 .INIT=16'hFFF8; LUT3 \spiflash_inst/u_spi_ctrl/tx_ptr_4_s1 ( .I0(\spiflash_inst/u_spi_ctrl/n954_2 ), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [4]), .I2(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/tx_ptr [4]) ); defparam \spiflash_inst/u_spi_ctrl/tx_ptr_4_s1 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/tx_ptr_3_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n955_2 ), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [3]), .I2(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/tx_ptr [3]) ); defparam \spiflash_inst/u_spi_ctrl/tx_ptr_3_s0 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/tx_ptr_2_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n956_2 ), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [2]), .I2(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/tx_ptr [2]) ); defparam \spiflash_inst/u_spi_ctrl/tx_ptr_2_s0 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/tx_ptr_1_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n957_2 ), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [1]), .I2(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/tx_ptr [1]) ); defparam \spiflash_inst/u_spi_ctrl/tx_ptr_1_s0 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/tx_ptr_0_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n958_2 ), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [0]), .I2(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/tx_ptr [0]) ); defparam \spiflash_inst/u_spi_ctrl/tx_ptr_0_s0 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/rx_ptr_4_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n1002_2 ), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [4]), .I2(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/rx_ptr [4]) ); defparam \spiflash_inst/u_spi_ctrl/rx_ptr_4_s0 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/rx_ptr_3_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n1003_2 ), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]), .I2(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/rx_ptr [3]) ); defparam \spiflash_inst/u_spi_ctrl/rx_ptr_3_s0 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/rx_ptr_2_s0 ( .I0(\spiflash_inst/u_spi_ctrl/n1004_2 ), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [2]), .I2(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/rx_ptr [2]) ); defparam \spiflash_inst/u_spi_ctrl/rx_ptr_2_s0 .INIT=8'hCA; LUT2 \spiflash_inst/u_spi_ctrl/rxf_wr_Z_s0 ( .I0(\spiflash_inst/rxf_full ), .I1(\spiflash_inst/rx_shift_reg_full_r ), .F(\spiflash_inst/rxf_wr_Z ) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_Z_s0 .INIT=4'h4; LUT2 \spiflash_inst/u_spi_ctrl/n242_s17 ( .I0(\spiflash_inst/n242_23 ), .I1(\spiflash_inst/n242_24 ), .F(\spiflash_inst/u_spi_ctrl/n242_22 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s17 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_ctrl/n243_s16 ( .I0(\spiflash_inst/arb_trans_end_sclk_Z_3 ), .I1(\spiflash_inst/u_spi_ctrl/n243_22 ), .I2(\spiflash_inst/u_spi_ctrl/n243_23 ), .I3(\spiflash_inst/u_spi_ctrl/n243_24 ), .F(\spiflash_inst/n243_21 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s16 .INIT=16'hFFE0; LUT4 \spiflash_inst/u_spi_ctrl/n244_s18 ( .I0(\spiflash_inst/u_spi_ctrl/n244_25 ), .I1(\spiflash_inst/u_spi_ctrl/n244_26 ), .I2(\spiflash_inst/u_spi_ctrl/n244_27 ), .I3(\spiflash_inst/u_spi_ctrl/n244_28 ), .F(\spiflash_inst/n244_24 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s18 .INIT=16'h0D00; LUT3 \spiflash_inst/u_spi_ctrl/n245_s16 ( .I0(\spiflash_inst/u_spi_ctrl/n245_22 ), .I1(\spiflash_inst/u_spi_ctrl/n245_23 ), .I2(\spiflash_inst/u_spi_ctrl/n245_24 ), .F(\spiflash_inst/n245_21 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s16 .INIT=8'h10; LUT3 \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_s3 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_13 ), .I2(\spiflash_inst/rx_bit_cnt_r_4_11 ), .F(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_8 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_s3 .INIT=8'hFE; LUT4 \spiflash_inst/u_spi_ctrl/tx_ready_s3 ( .I0(\spiflash_inst/u_spi_ctrl/tx_ready_9 ), .I1(\spiflash_inst/spi_txdata_rd_Z ), .I2(\spiflash_inst/txf_rd_Z ), .I3(\spiflash_inst/u_spi_ctrl/tx_ready_10 ), .F(\spiflash_inst/u_spi_ctrl/tx_ready_8 ) ); defparam \spiflash_inst/u_spi_ctrl/tx_ready_s3 .INIT=16'hF8FF; LUT2 \spiflash_inst/u_spi_ctrl/tx_mux_r_31_s3 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ), .I1(\spiflash_inst/txf_rd_Z ), .F(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_31_s3 .INIT=4'hE; LUT3 \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_s5 ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_11 ), .I1(\spiflash_inst/arb_addr_len [1]), .I2(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_12 ), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len [4]) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_s5 .INIT=8'hF8; LUT3 \spiflash_inst/u_spi_ctrl/ctrl_word_len_3_s5 ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_11 ), .I1(\spiflash_inst/arb_addr_len [0]), .I2(\spiflash_inst/u_spi_ctrl/ctrl_word_len_3_11 ), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len [3]) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_3_s5 .INIT=8'hF8; LUT3 \spiflash_inst/u_spi_ctrl/n563_s2 ( .I0(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [1]), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [0]), .I2(\spiflash_inst/u_spi_ctrl/n564_7 ), .F(\spiflash_inst/u_spi_ctrl/n563_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n563_s2 .INIT=8'h60; LUT4 \spiflash_inst/u_spi_ctrl/n562_s2 ( .I0(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [1]), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [0]), .I2(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [2]), .I3(\spiflash_inst/u_spi_ctrl/n564_7 ), .F(\spiflash_inst/u_spi_ctrl/n562_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n562_s2 .INIT=16'h7800; LUT3 \spiflash_inst/u_spi_ctrl/n560_s2 ( .I0(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [4]), .I1(\spiflash_inst/u_spi_ctrl/n560_7 ), .I2(\spiflash_inst/u_spi_ctrl/n564_7 ), .F(\spiflash_inst/u_spi_ctrl/n560_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n560_s2 .INIT=8'h60; LUT4 \spiflash_inst/u_spi_ctrl/n522_s3 ( .I0(\spiflash_inst/u_spi_ctrl/n522_8 ), .I1(\spiflash_inst/u_spi_ctrl/n522_9 ), .I2(\spiflash_inst/u_spi_ctrl/n522_10 ), .I3(\spiflash_inst/u_spi_ctrl/n522_13 ), .F(\spiflash_inst/u_spi_ctrl/n522_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n522_s3 .INIT=16'hFFE0; LUT4 \spiflash_inst/u_spi_ctrl/n521_s4 ( .I0(\spiflash_inst/u_spi_ctrl/n522_8 ), .I1(\spiflash_inst/u_spi_ctrl/n522_9 ), .I2(\spiflash_inst/u_spi_ctrl/n521_9 ), .I3(\spiflash_inst/u_spi_ctrl/n521_12 ), .F(\spiflash_inst/u_spi_ctrl/n521_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n521_s4 .INIT=16'hFFE0; LUT2 \spiflash_inst/u_spi_ctrl/n455_s2 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/n455_9 ), .F(\spiflash_inst/u_spi_ctrl/n455_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n455_s2 .INIT=4'h4; LUT3 \spiflash_inst/u_spi_ctrl/n454_s2 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [1]), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [0]), .I2(\spiflash_inst/u_spi_ctrl/n455_9 ), .F(\spiflash_inst/u_spi_ctrl/n454_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n454_s2 .INIT=8'h60; LUT4 \spiflash_inst/u_spi_ctrl/n453_s2 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [1]), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [0]), .I2(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [2]), .I3(\spiflash_inst/u_spi_ctrl/n455_9 ), .F(\spiflash_inst/u_spi_ctrl/n453_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n453_s2 .INIT=16'h7800; LUT2 \spiflash_inst/u_spi_ctrl/n452_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n452_7 ), .I1(\spiflash_inst/u_spi_ctrl/n455_9 ), .F(\spiflash_inst/u_spi_ctrl/n452_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n452_s2 .INIT=4'h8; LUT3 \spiflash_inst/u_spi_ctrl/n451_s2 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [4]), .I1(\spiflash_inst/u_spi_ctrl/n451_7 ), .I2(\spiflash_inst/u_spi_ctrl/n455_9 ), .F(\spiflash_inst/u_spi_ctrl/n451_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n451_s2 .INIT=8'h60; LUT3 \spiflash_inst/u_spi_ctrl/n354_s2 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/data_cnt_r [1]), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ), .F(\spiflash_inst/u_spi_ctrl/n354_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n354_s2 .INIT=8'h60; LUT4 \spiflash_inst/u_spi_ctrl/n352_s2 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [2]), .I1(\spiflash_inst/u_spi_ctrl/n353_7 ), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r [3]), .I3(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ), .F(\spiflash_inst/u_spi_ctrl/n352_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n352_s2 .INIT=16'h7800; LUT3 \spiflash_inst/u_spi_ctrl/n351_s2 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [4]), .I1(\spiflash_inst/u_spi_ctrl/n351_9 ), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ), .F(\spiflash_inst/u_spi_ctrl/n351_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n351_s2 .INIT=8'h60; LUT4 \spiflash_inst/u_spi_ctrl/n350_s2 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [4]), .I1(\spiflash_inst/u_spi_ctrl/n351_9 ), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r [5]), .I3(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ), .F(\spiflash_inst/u_spi_ctrl/n350_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n350_s2 .INIT=16'h7800; LUT4 \spiflash_inst/u_spi_ctrl/n349_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n351_9 ), .I1(\spiflash_inst/u_spi_ctrl/n349_7 ), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r [6]), .I3(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ), .F(\spiflash_inst/u_spi_ctrl/n349_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n349_s2 .INIT=16'h7800; LUT3 \spiflash_inst/u_spi_ctrl/n348_s2 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [7]), .I1(\spiflash_inst/u_spi_ctrl/n348_9 ), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ), .F(\spiflash_inst/u_spi_ctrl/n348_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n348_s2 .INIT=8'h60; LUT4 \spiflash_inst/u_spi_ctrl/n347_s2 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [7]), .I1(\spiflash_inst/u_spi_ctrl/n348_9 ), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r [8]), .I3(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ), .F(\spiflash_inst/u_spi_ctrl/n347_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n347_s2 .INIT=16'h7800; LUT2 \spiflash_inst/u_spi_ctrl/n296_s2 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/n244_24 ), .F(\spiflash_inst/u_spi_ctrl/n296_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n296_s2 .INIT=4'h4; LUT2 \spiflash_inst/u_spi_ctrl/n295_s2 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/n243_21 ), .F(\spiflash_inst/u_spi_ctrl/n295_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n295_s2 .INIT=4'h4; LUT2 \spiflash_inst/u_spi_ctrl/n21_s2 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/arb_req_sclk ), .F(\spiflash_inst/u_spi_ctrl/n21_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n21_s2 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_ctrl/arb_trans_end_sclk_Z_s0 ( .I0(\spiflash_inst/ctrl_cs_r [0]), .I1(\spiflash_inst/ctrl_cs_r [1]), .I2(\spiflash_inst/ctrl_cs_r [2]), .I3(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/arb_trans_end_sclk_Z_3 ) ); defparam \spiflash_inst/u_spi_ctrl/arb_trans_end_sclk_Z_s0 .INIT=16'h0001; LUT4 \spiflash_inst/u_spi_ctrl/arb_trans_end_sclk_Z_s1 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/n243_21 ), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n242_22 ), .F(\spiflash_inst/arb_trans_end_sclk_Z_4 ) ); defparam \spiflash_inst/u_spi_ctrl/arb_trans_end_sclk_Z_s1 .INIT=16'h0001; LUT2 \spiflash_inst/u_spi_ctrl/n306_s1 ( .I0(\spiflash_inst/spi_cs_r [2]), .I1(\spiflash_inst/spi_cs_r [1]), .F(\spiflash_inst/n306_4 ) ); defparam \spiflash_inst/u_spi_ctrl/n306_s1 .INIT=4'h1; LUT3 \spiflash_inst/u_spi_ctrl/txf_rd_Z_s0 ( .I0(\spiflash_inst/n242_24 ), .I1(\spiflash_inst/n242_23 ), .I2(\spiflash_inst/txf_rd_Z_4 ), .F(\spiflash_inst/u_spi_ctrl/txf_rd_Z_3 ) ); defparam \spiflash_inst/u_spi_ctrl/txf_rd_Z_s0 .INIT=8'hE0; LUT3 \spiflash_inst/u_spi_ctrl/n852_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/n245_21 ), .I2(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n852_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n852_s2 .INIT=8'h40; LUT4 \spiflash_inst/u_spi_ctrl/n853_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [30]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n853_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n853_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n853_s3 ( .I0(\spiflash_inst/arb_trans_ctrl [11]), .I1(\spiflash_inst/n244_24 ), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n853_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n853_s3 .INIT=16'h8000; LUT4 \spiflash_inst/u_spi_ctrl/n854_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [29]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n854_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n854_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n856_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [27]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n856_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n856_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n859_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [24]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n859_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n859_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n861_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [22]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n861_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n861_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n862_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [21]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n862_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n862_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n864_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [19]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n864_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n864_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n867_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [16]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n867_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n867_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n869_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [14]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n869_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n869_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n870_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [13]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n870_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n870_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n872_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [11]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n872_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n872_s2 .INIT=16'h4000; LUT4 \spiflash_inst/u_spi_ctrl/n875_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/arb_addr [8]), .I2(\spiflash_inst/n245_21 ), .I3(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n875_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n875_s2 .INIT=16'h4000; LUT3 \spiflash_inst/u_spi_ctrl/n876_s1 ( .I0(\spiflash_inst/arb_addr [7]), .I1(\spiflash_inst/arb_opcode [7]), .I2(\spiflash_inst/n245_21 ), .F(\spiflash_inst/u_spi_ctrl/n876_4 ) ); defparam \spiflash_inst/u_spi_ctrl/n876_s1 .INIT=8'hAC; LUT3 \spiflash_inst/u_spi_ctrl/n877_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/u_spi_ctrl/n877_6 ), .I2(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n877_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n877_s2 .INIT=8'h40; LUT3 \spiflash_inst/u_spi_ctrl/n878_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/u_spi_ctrl/n878_6 ), .I2(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n878_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n878_s2 .INIT=8'h40; LUT3 \spiflash_inst/u_spi_ctrl/n879_s1 ( .I0(\spiflash_inst/arb_addr [4]), .I1(\spiflash_inst/arb_opcode [4]), .I2(\spiflash_inst/n245_21 ), .F(\spiflash_inst/u_spi_ctrl/n879_4 ) ); defparam \spiflash_inst/u_spi_ctrl/n879_s1 .INIT=8'hAC; LUT3 \spiflash_inst/u_spi_ctrl/n880_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/u_spi_ctrl/n880_6 ), .I2(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n880_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n880_s2 .INIT=8'h40; LUT3 \spiflash_inst/u_spi_ctrl/n881_s1 ( .I0(\spiflash_inst/arb_addr [2]), .I1(\spiflash_inst/arb_opcode [2]), .I2(\spiflash_inst/n245_21 ), .F(\spiflash_inst/u_spi_ctrl/n881_4 ) ); defparam \spiflash_inst/u_spi_ctrl/n881_s1 .INIT=8'hAC; LUT3 \spiflash_inst/u_spi_ctrl/n882_s1 ( .I0(\spiflash_inst/arb_addr [1]), .I1(\spiflash_inst/arb_opcode [1]), .I2(\spiflash_inst/n245_21 ), .F(\spiflash_inst/u_spi_ctrl/n882_4 ) ); defparam \spiflash_inst/u_spi_ctrl/n882_s1 .INIT=8'hAC; LUT3 \spiflash_inst/u_spi_ctrl/n883_s2 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/u_spi_ctrl/n883_6 ), .I2(\spiflash_inst/u_spi_ctrl/n852_9 ), .F(\spiflash_inst/u_spi_ctrl/n883_5 ) ); defparam \spiflash_inst/u_spi_ctrl/n883_s2 .INIT=8'h40; LUT2 \spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [1]), .F(\spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_3 ) ); defparam \spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_s0 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_s1 ( .I0(\spiflash_inst/ctrl_cs_r [3]), .I1(\spiflash_inst/ctrl_cs_r [0]), .I2(\spiflash_inst/ctrl_cs_r [2]), .I3(\spiflash_inst/ctrl_cs_r [1]), .F(\spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_4 ) ); defparam \spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_s1 .INIT=16'h0130; LUT2 \spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_s2 ( .I0(\spiflash_inst/rxf_full ), .I1(\spiflash_inst/rx_shift_reg_full_r ), .F(\spiflash_inst/spi_rx_hold_Z_5 ) ); defparam \spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_s2 .INIT=4'h8; LUT4 \spiflash_inst/u_spi_ctrl/n242_s18 ( .I0(\spiflash_inst/spi_txdata_rd_Z ), .I1(\spiflash_inst/u_spi_ctrl/n242_25 ), .I2(\spiflash_inst/u_spi_ctrl/n242_42 ), .I3(\spiflash_inst/u_spi_ctrl/n242_44 ), .F(\spiflash_inst/n242_23 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s18 .INIT=16'hF800; LUT4 \spiflash_inst/u_spi_ctrl/n242_s19 ( .I0(\spiflash_inst/u_spi_ctrl/n242_46 ), .I1(\spiflash_inst/u_spi_ctrl/n242_38 ), .I2(\spiflash_inst/ctrl_cs_r [2]), .I3(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/n242_24 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s19 .INIT=16'hA0F3; LUT2 \spiflash_inst/u_spi_ctrl/n243_s17 ( .I0(\spiflash_inst/spi_txdata_rd_Z ), .I1(\spiflash_inst/u_spi_ctrl/n243_25 ), .F(\spiflash_inst/u_spi_ctrl/n243_22 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s17 .INIT=4'h8; LUT3 \spiflash_inst/u_spi_ctrl/n243_s18 ( .I0(\spiflash_inst/u_spi_ctrl/n243_26 ), .I1(\spiflash_inst/u_spi_ctrl/n243_27 ), .I2(\spiflash_inst/u_spi_ctrl/n243_28 ), .F(\spiflash_inst/u_spi_ctrl/n243_23 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s18 .INIT=8'h0E; LUT4 \spiflash_inst/u_spi_ctrl/n243_s19 ( .I0(\spiflash_inst/u_spi_ctrl/n243_29 ), .I1(\spiflash_inst/u_spi_ctrl/n243_46 ), .I2(\spiflash_inst/ctrl_cs_r [3]), .I3(\spiflash_inst/ctrl_cs_r [2]), .F(\spiflash_inst/u_spi_ctrl/n243_24 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s19 .INIT=16'h3500; LUT4 \spiflash_inst/u_spi_ctrl/n244_s19 ( .I0(\spiflash_inst/spi_txdata_rd_Z ), .I1(\spiflash_inst/u_spi_ctrl/n243_25 ), .I2(\spiflash_inst/u_spi_ctrl/n244_29 ), .I3(\spiflash_inst/u_spi_ctrl/n244_30 ), .F(\spiflash_inst/u_spi_ctrl/n244_25 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s19 .INIT=16'h7F00; LUT4 \spiflash_inst/u_spi_ctrl/n244_s20 ( .I0(\spiflash_inst/u_spi_ctrl/n244_65 ), .I1(\spiflash_inst/spi_txdata_rd_Z ), .I2(\spiflash_inst/ctrl_cs_r [0]), .I3(\spiflash_inst/ctrl_cs_r [1]), .F(\spiflash_inst/u_spi_ctrl/n244_26 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s20 .INIT=16'h7000; LUT4 \spiflash_inst/u_spi_ctrl/n244_s21 ( .I0(\spiflash_inst/spi_txdata_rd_Z ), .I1(\spiflash_inst/u_spi_ctrl/n244_32 ), .I2(\spiflash_inst/ctrl_cs_r [1]), .I3(\spiflash_inst/u_spi_ctrl/n244_59 ), .F(\spiflash_inst/u_spi_ctrl/n244_27 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s21 .INIT=16'h8700; LUT4 \spiflash_inst/u_spi_ctrl/n244_s22 ( .I0(\spiflash_inst/spi_txdata_rd_Z ), .I1(\spiflash_inst/u_spi_ctrl/n244_34 ), .I2(\spiflash_inst/n244_35 ), .I3(\spiflash_inst/u_spi_ctrl/n244_36 ), .F(\spiflash_inst/u_spi_ctrl/n244_28 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s22 .INIT=16'h8F00; LUT4 \spiflash_inst/u_spi_ctrl/n245_s17 ( .I0(\spiflash_inst/u_spi_ctrl/n243_25 ), .I1(\spiflash_inst/u_spi_ctrl/n245_25 ), .I2(\spiflash_inst/spi_txdata_rd_Z ), .I3(\spiflash_inst/u_spi_ctrl/n522_9 ), .F(\spiflash_inst/u_spi_ctrl/n245_22 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s17 .INIT=16'hDF00; LUT4 \spiflash_inst/u_spi_ctrl/n245_s18 ( .I0(\spiflash_inst/u_spi_ctrl/n245_26 ), .I1(\spiflash_inst/u_spi_ctrl/n245_40 ), .I2(\spiflash_inst/spi_txdata_rd_Z ), .I3(\spiflash_inst/u_spi_ctrl/n243_25 ), .F(\spiflash_inst/u_spi_ctrl/n245_23 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s18 .INIT=16'h5CCC; LUT4 \spiflash_inst/u_spi_ctrl/n245_s19 ( .I0(\spiflash_inst/u_spi_ctrl/n243_25 ), .I1(\spiflash_inst/spi_txdata_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/n245_28 ), .I3(\spiflash_inst/u_spi_ctrl/n245_29 ), .F(\spiflash_inst/u_spi_ctrl/n245_24 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s19 .INIT=16'h7F00; LUT4 \spiflash_inst/u_spi_ctrl/data_cnt_r_8_s4 ( .I0(\spiflash_inst/ctrl_cs_r [3]), .I1(\spiflash_inst/ctrl_cs_r [2]), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_11 ), .I3(\spiflash_inst/u_spi_ctrl/n243_25 ), .F(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_9 ) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_8_s4 .INIT=16'h4100; LUT2 \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_s4 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ), .F(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_9 ) ); defparam \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_s4 .INIT=4'h1; LUT3 \spiflash_inst/u_spi_ctrl/tx_ready_s4 ( .I0(\spiflash_inst/u_spi_ctrl/tx_ready_11 ), .I1(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .I2(\spiflash_inst/u_spi_ctrl/n243_25 ), .F(\spiflash_inst/u_spi_ctrl/tx_ready_9 ) ); defparam \spiflash_inst/u_spi_ctrl/tx_ready_s4 .INIT=8'hD0; LUT2 \spiflash_inst/u_spi_ctrl/tx_ready_s5 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/spi_ns_2_21 ), .F(\spiflash_inst/u_spi_ctrl/tx_ready_10 ) ); defparam \spiflash_inst/u_spi_ctrl/tx_ready_s5 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_s6 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/ctrl_cs_r [2]), .I2(\spiflash_inst/ctrl_cs_r [0]), .I3(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_11 ) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_s6 .INIT=16'h1000; LUT4 \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_s7 ( .I0(\spiflash_inst/spi_data_len [3]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_13 ), .I2(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_14 ), .I3(\spiflash_inst/u_spi_ctrl/ctrl_word_len_0_6 ), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_12 ) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_s7 .INIT=16'h004F; LUT4 \spiflash_inst/u_spi_ctrl/ctrl_word_len_3_s6 ( .I0(\spiflash_inst/spi_data_len [4]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_13 ), .I2(\spiflash_inst/u_spi_ctrl/ctrl_word_len_3_12 ), .I3(\spiflash_inst/u_spi_ctrl/ctrl_word_len_0_6 ), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len_3_11 ) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_3_s6 .INIT=16'h004F; LUT4 \spiflash_inst/u_spi_ctrl/n1079_s2 ( .I0(\spiflash_inst/spi_rxdata_Z [0]), .I1(\spiflash_inst/u_spi_ctrl/n1018_19 ), .I2(\spiflash_inst/u_spi_ctrl/n1079_7 ), .I3(\spiflash_inst/u_spi_ctrl/n1079_8 ), .F(\spiflash_inst/u_spi_ctrl/n1079_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n1079_s2 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n1078_s2 ( .I0(\spiflash_inst/spi_rxdata_Z [0]), .I1(\spiflash_inst/u_spi_ctrl/n1022_19 ), .I2(\spiflash_inst/u_spi_ctrl/n1079_8 ), .I3(\spiflash_inst/u_spi_ctrl/n1079_7 ), .F(\spiflash_inst/u_spi_ctrl/n1078_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n1078_s2 .INIT=16'hCCAC; LUT4 \spiflash_inst/u_spi_ctrl/n1077_s2 ( .I0(\spiflash_inst/spi_rxdata_Z [0]), .I1(\spiflash_inst/u_spi_ctrl/n1026_19 ), .I2(\spiflash_inst/u_spi_ctrl/n1079_7 ), .I3(\spiflash_inst/u_spi_ctrl/n1079_8 ), .F(\spiflash_inst/u_spi_ctrl/n1077_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n1077_s2 .INIT=16'hCCAC; LUT4 \spiflash_inst/u_spi_ctrl/n1076_s2 ( .I0(\spiflash_inst/spi_rxdata_Z [0]), .I1(\spiflash_inst/u_spi_ctrl/n1030_19 ), .I2(\spiflash_inst/u_spi_ctrl/n1079_7 ), .I3(\spiflash_inst/u_spi_ctrl/n1079_8 ), .F(\spiflash_inst/u_spi_ctrl/n1076_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n1076_s2 .INIT=16'hACCC; LUT3 \spiflash_inst/u_spi_ctrl/n564_s3 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_11 ), .I2(\spiflash_inst/rx_bit_cnt_r_4_11 ), .F(\spiflash_inst/u_spi_ctrl/n564_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n564_s3 .INIT=8'h01; LUT4 \spiflash_inst/u_spi_ctrl/n561_s3 ( .I0(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [2]), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [1]), .I2(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [0]), .I3(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]), .F(\spiflash_inst/u_spi_ctrl/n561_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n561_s3 .INIT=16'h7F80; LUT4 \spiflash_inst/u_spi_ctrl/n560_s3 ( .I0(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [2]), .I2(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [1]), .I3(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [0]), .F(\spiflash_inst/u_spi_ctrl/n560_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n560_s3 .INIT=16'h8000; LUT4 \spiflash_inst/u_spi_ctrl/n522_s4 ( .I0(\spiflash_inst/n245_21 ), .I1(\spiflash_inst/u_spi_ctrl/n242_22 ), .I2(\spiflash_inst/n244_24 ), .I3(\spiflash_inst/n243_21 ), .F(\spiflash_inst/u_spi_ctrl/n522_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n522_s4 .INIT=16'h0110; LUT4 \spiflash_inst/u_spi_ctrl/n522_s5 ( .I0(\spiflash_inst/ctrl_cs_r [0]), .I1(\spiflash_inst/ctrl_cs_r [3]), .I2(\spiflash_inst/ctrl_cs_r [1]), .I3(\spiflash_inst/ctrl_cs_r [2]), .F(\spiflash_inst/u_spi_ctrl/n522_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n522_s5 .INIT=16'h0110; LUT3 \spiflash_inst/u_spi_ctrl/n522_s6 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_ctrl/n489_7 ), .I2(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ), .F(\spiflash_inst/u_spi_ctrl/n522_10 ) ); defparam \spiflash_inst/u_spi_ctrl/n522_s6 .INIT=8'h40; LUT3 \spiflash_inst/u_spi_ctrl/n521_s5 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_ctrl/n488_7 ), .I2(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ), .F(\spiflash_inst/u_spi_ctrl/n521_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n521_s5 .INIT=8'h40; LUT4 \spiflash_inst/u_spi_ctrl/n452_s3 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [2]), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [1]), .I2(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [0]), .I3(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [3]), .F(\spiflash_inst/u_spi_ctrl/n452_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n452_s3 .INIT=16'h7F80; LUT4 \spiflash_inst/u_spi_ctrl/n451_s3 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [3]), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [2]), .I2(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [1]), .I3(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [0]), .F(\spiflash_inst/u_spi_ctrl/n451_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n451_s3 .INIT=16'h8000; LUT2 \spiflash_inst/u_spi_ctrl/n353_s3 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/data_cnt_r [1]), .F(\spiflash_inst/u_spi_ctrl/n353_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n353_s3 .INIT=4'h8; LUT2 \spiflash_inst/u_spi_ctrl/n349_s3 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [4]), .I1(\spiflash_inst/u_spi_ctrl/data_cnt_r [5]), .F(\spiflash_inst/u_spi_ctrl/n349_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n349_s3 .INIT=4'h8; LUT3 \spiflash_inst/u_spi_ctrl/n489_s3 ( .I0(\spiflash_inst/u_spi_ctrl/tx_rx_diff_cnt_r [0]), .I1(\spiflash_inst/spi_txdata_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_13 ), .F(\spiflash_inst/u_spi_ctrl/n489_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n489_s3 .INIT=8'h96; LUT4 \spiflash_inst/u_spi_ctrl/n488_s3 ( .I0(\spiflash_inst/u_spi_ctrl/tx_rx_diff_cnt_r [0]), .I1(\spiflash_inst/spi_txdata_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_13 ), .I3(\spiflash_inst/u_spi_ctrl/tx_rx_diff_cnt_r [1]), .F(\spiflash_inst/u_spi_ctrl/n488_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n488_s3 .INIT=16'hE718; LUT4 \spiflash_inst/u_spi_ctrl/ctrl_word_len_0_s2 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/ctrl_cs_r [0]), .I2(\spiflash_inst/ctrl_cs_r [2]), .I3(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len_0_6 ) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_0_s2 .INIT=16'h0D00; LUT2 \spiflash_inst/u_spi_ctrl/ctrl_word_len_0_s3 ( .I0(\spiflash_inst/arb_cs_r [1]), .I1(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/ctrl_word_len_0_7 ) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_0_s3 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_ctrl/txf_rd_Z_s1 ( .I0(\spiflash_inst/spi_txdata_rd_Z ), .I1(\spiflash_inst/u_spi_ctrl/tx_ready_9 ), .I2(\spiflash_inst/tx_ready ), .I3(\spiflash_inst/txf_empty ), .F(\spiflash_inst/txf_rd_Z_4 ) ); defparam \spiflash_inst/u_spi_ctrl/txf_rd_Z_s1 .INIT=16'h008F; LUT4 \spiflash_inst/u_spi_ctrl/n877_s3 ( .I0(\spiflash_inst/arb_addr [6]), .I1(\spiflash_inst/arb_opcode [6]), .I2(\spiflash_inst/u_spi_ctrl/n245_24 ), .I3(\spiflash_inst/u_spi_ctrl/n245_23 ), .F(\spiflash_inst/u_spi_ctrl/n877_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n877_s3 .INIT=16'hCCAC; LUT4 \spiflash_inst/u_spi_ctrl/n878_s3 ( .I0(\spiflash_inst/arb_addr [5]), .I1(\spiflash_inst/arb_opcode [5]), .I2(\spiflash_inst/u_spi_ctrl/n245_24 ), .I3(\spiflash_inst/u_spi_ctrl/n245_23 ), .F(\spiflash_inst/u_spi_ctrl/n878_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n878_s3 .INIT=16'hCCAC; LUT4 \spiflash_inst/u_spi_ctrl/n880_s3 ( .I0(\spiflash_inst/arb_addr [3]), .I1(\spiflash_inst/arb_opcode [3]), .I2(\spiflash_inst/u_spi_ctrl/n245_24 ), .I3(\spiflash_inst/u_spi_ctrl/n245_23 ), .F(\spiflash_inst/u_spi_ctrl/n880_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n880_s3 .INIT=16'hCCAC; LUT4 \spiflash_inst/u_spi_ctrl/n883_s3 ( .I0(\spiflash_inst/arb_addr [0]), .I1(\spiflash_inst/arb_opcode [0]), .I2(\spiflash_inst/u_spi_ctrl/n245_24 ), .I3(\spiflash_inst/u_spi_ctrl/n245_23 ), .F(\spiflash_inst/u_spi_ctrl/n883_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n883_s3 .INIT=16'hCCAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_s1 ( .I0(\spiflash_inst/spi_data_len [4]), .I1(\spiflash_inst/spi_data_len [3]), .I2(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_13 ), .I3(\spiflash_inst/ctrl_word_len_0_7 ), .F(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_s1 .INIT=16'hEF00; LUT2 \spiflash_inst/u_spi_ctrl/n242_s20 ( .I0(\spiflash_inst/u_spi_ctrl/n243_25 ), .I1(\spiflash_inst/u_spi_ctrl/n242_30 ), .F(\spiflash_inst/u_spi_ctrl/n242_25 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s20 .INIT=4'h8; LUT4 \spiflash_inst/u_spi_ctrl/n243_s20 ( .I0(\spiflash_inst/u_spi_ctrl/n243_31 ), .I1(\spiflash_inst/u_spi_ctrl/n243_32 ), .I2(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .I3(\spiflash_inst/u_spi_ctrl/n597_3 ), .F(\spiflash_inst/u_spi_ctrl/n243_25 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s20 .INIT=16'h008F; LUT4 \spiflash_inst/u_spi_ctrl/n243_s21 ( .I0(\spiflash_inst/u_spi_ctrl/n243_33 ), .I1(\spiflash_inst/u_spi_ctrl/n277_3 ), .I2(\spiflash_inst/ctrl_cs_r [1]), .I3(\spiflash_inst/u_spi_ctrl/n243_34 ), .F(\spiflash_inst/u_spi_ctrl/n243_26 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s21 .INIT=16'h3500; LUT4 \spiflash_inst/u_spi_ctrl/n243_s22 ( .I0(\spiflash_inst/u_spi_ctrl/n242_36 ), .I1(\spiflash_inst/ctrl_cs_r [0]), .I2(\spiflash_inst/ctrl_cs_r [1]), .I3(\spiflash_inst/u_spi_ctrl/n244_30 ), .F(\spiflash_inst/u_spi_ctrl/n243_27 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s22 .INIT=16'hCA00; LUT4 \spiflash_inst/u_spi_ctrl/n243_s23 ( .I0(\spiflash_inst/u_spi_ctrl/n243_35 ), .I1(\spiflash_inst/u_spi_ctrl/n243_36 ), .I2(\spiflash_inst/u_spi_ctrl/n243_37 ), .I3(\spiflash_inst/u_spi_ctrl/n243_38 ), .F(\spiflash_inst/u_spi_ctrl/n243_28 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s23 .INIT=16'h0305; LUT3 \spiflash_inst/u_spi_ctrl/n243_s24 ( .I0(\spiflash_inst/rx_shift_reg_full_r ), .I1(\spiflash_inst/ctrl_cs_r [1]), .I2(\spiflash_inst/ctrl_cs_r [0]), .F(\spiflash_inst/u_spi_ctrl/n243_29 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s24 .INIT=8'h40; LUT4 \spiflash_inst/u_spi_ctrl/n244_s23 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/u_spi_ctrl/tx_ready_11 ), .I2(\spiflash_inst/u_spi_ctrl/n244_37 ), .I3(\spiflash_inst/u_spi_ctrl/n244_38 ), .F(\spiflash_inst/u_spi_ctrl/n244_29 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s23 .INIT=16'h0001; LUT2 \spiflash_inst/u_spi_ctrl/n244_s24 ( .I0(\spiflash_inst/ctrl_cs_r [2]), .I1(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/u_spi_ctrl/n244_30 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s24 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_ctrl/n244_s26 ( .I0(\spiflash_inst/u_spi_ctrl/n244_40 ), .I1(\spiflash_inst/u_spi_ctrl/n244_57 ), .I2(\spiflash_inst/u_spi_ctrl/n244_39 ), .I3(\spiflash_inst/u_spi_ctrl/n243_25 ), .F(\spiflash_inst/u_spi_ctrl/n244_32 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s26 .INIT=16'hCA00; LUT2 \spiflash_inst/u_spi_ctrl/n244_s28 ( .I0(\spiflash_inst/u_spi_ctrl/n263_3 ), .I1(\spiflash_inst/u_spi_ctrl/n243_25 ), .F(\spiflash_inst/u_spi_ctrl/n244_34 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s28 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_ctrl/n244_s29 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/ctrl_cs_r [3]), .I2(\spiflash_inst/ctrl_cs_r [0]), .I3(\spiflash_inst/ctrl_cs_r [2]), .F(\spiflash_inst/n244_35 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s29 .INIT=16'h0110; LUT4 \spiflash_inst/u_spi_ctrl/n244_s30 ( .I0(\spiflash_inst/u_spi_ctrl/n243_29 ), .I1(\spiflash_inst/u_spi_ctrl/n244_43 ), .I2(\spiflash_inst/u_spi_ctrl/n244_44 ), .I3(\spiflash_inst/u_spi_ctrl/n244_45 ), .F(\spiflash_inst/u_spi_ctrl/n244_36 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s30 .INIT=16'h001F; LUT3 \spiflash_inst/u_spi_ctrl/n245_s20 ( .I0(\spiflash_inst/u_spi_ctrl/n277_3 ), .I1(\spiflash_inst/u_spi_ctrl/n245_30 ), .I2(\spiflash_inst/ctrl_cs_r [0]), .F(\spiflash_inst/u_spi_ctrl/n245_25 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s20 .INIT=8'h3A; LUT3 \spiflash_inst/u_spi_ctrl/n245_s21 ( .I0(\spiflash_inst/u_spi_ctrl/n242_44 ), .I1(\spiflash_inst/u_spi_ctrl/n245_31 ), .I2(\spiflash_inst/u_spi_ctrl/n242_42 ), .F(\spiflash_inst/u_spi_ctrl/n245_26 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s21 .INIT=8'h07; LUT4 \spiflash_inst/u_spi_ctrl/n245_s23 ( .I0(\spiflash_inst/u_spi_ctrl/n244_57 ), .I1(\spiflash_inst/u_spi_ctrl/n244_40 ), .I2(\spiflash_inst/u_spi_ctrl/n243_34 ), .I3(\spiflash_inst/u_spi_ctrl/n245_31 ), .F(\spiflash_inst/u_spi_ctrl/n245_28 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s23 .INIT=16'hE000; LUT4 \spiflash_inst/u_spi_ctrl/n245_s24 ( .I0(\spiflash_inst/u_spi_ctrl/n245_32 ), .I1(\spiflash_inst/u_spi_ctrl/n242_31 ), .I2(\spiflash_inst/u_spi_ctrl/n245_33 ), .I3(\spiflash_inst/u_spi_ctrl/n245_34 ), .F(\spiflash_inst/u_spi_ctrl/n245_29 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s24 .INIT=16'h004F; LUT2 \spiflash_inst/u_spi_ctrl/data_cnt_r_8_s6 ( .I0(\spiflash_inst/ctrl_cs_r [0]), .I1(\spiflash_inst/ctrl_cs_r [1]), .F(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_11 ) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_8_s6 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_ctrl/tx_ready_s6 ( .I0(\spiflash_inst/u_spi_ctrl/tx_ready_12 ), .I1(\spiflash_inst/u_spi_ctrl/tx_ready_13 ), .I2(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_11 ), .I3(\spiflash_inst/u_spi_ctrl/tx_ready_14 ), .F(\spiflash_inst/u_spi_ctrl/tx_ready_11 ) ); defparam \spiflash_inst/u_spi_ctrl/tx_ready_s6 .INIT=16'h3500; LUT3 \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s6 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_12 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_14 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_11 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s6 .INIT=8'hE0; LUT4 \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_s8 ( .I0(\spiflash_inst/spi_data_len [0]), .I1(\spiflash_inst/spi_data_len [1]), .I2(\spiflash_inst/spi_data_len [2]), .I3(\spiflash_inst/reg_spi_format_r [5]), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_13 ) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_s8 .INIT=16'h8000; LUT3 \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_s9 ( .I0(\spiflash_inst/spi_data_len [4]), .I1(\spiflash_inst/arb_cs_r [1]), .I2(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_14 ) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_4_s9 .INIT=8'h01; LUT3 \spiflash_inst/u_spi_ctrl/ctrl_word_len_3_s7 ( .I0(\spiflash_inst/spi_data_len [3]), .I1(\spiflash_inst/arb_cs_r [1]), .I2(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len_3_12 ) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_3_s7 .INIT=8'h01; LUT3 \spiflash_inst/u_spi_ctrl/n1079_s3 ( .I0(\spiflash_inst/u_spi_ctrl/n1005_2 ), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [1]), .I2(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/n1079_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1079_s3 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_ctrl/n1079_s4 ( .I0(\spiflash_inst/u_spi_ctrl/n1006_2 ), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [0]), .I2(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/n1079_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n1079_s4 .INIT=8'hCA; LUT4 \spiflash_inst/u_spi_ctrl/n242_s25 ( .I0(\spiflash_inst/arb_trans_ctrl [24]), .I1(\spiflash_inst/arb_trans_ctrl [27]), .I2(\spiflash_inst/arb_trans_ctrl [25]), .I3(\spiflash_inst/arb_trans_ctrl [26]), .F(\spiflash_inst/u_spi_ctrl/n242_30 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s25 .INIT=16'h133F; LUT2 \spiflash_inst/u_spi_ctrl/n242_s26 ( .I0(\spiflash_inst/ctrl_cs_r [0]), .I1(\spiflash_inst/ctrl_cs_r [1]), .F(\spiflash_inst/u_spi_ctrl/n242_31 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s26 .INIT=4'h4; LUT2 \spiflash_inst/u_spi_ctrl/n242_s28 ( .I0(\spiflash_inst/arb_req_invalid ), .I1(\spiflash_inst/arb_req_sclk ), .F(\spiflash_inst/n242_33 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s28 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_ctrl/n243_s26 ( .I0(\spiflash_inst/arb_addr_len [0]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_11 ), .I2(\spiflash_inst/u_spi_ctrl/ctrl_word_len_3_11 ), .I3(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [3]), .F(\spiflash_inst/u_spi_ctrl/n243_31 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s26 .INIT=16'hF807; LUT4 \spiflash_inst/u_spi_ctrl/n243_s27 ( .I0(\spiflash_inst/arb_addr_len [1]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_11 ), .I2(\spiflash_inst/u_spi_ctrl/ctrl_word_len_4_12 ), .I3(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [4]), .F(\spiflash_inst/u_spi_ctrl/n243_32 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s27 .INIT=16'hF807; LUT4 \spiflash_inst/u_spi_ctrl/n243_s28 ( .I0(\spiflash_inst/n242_33 ), .I1(\spiflash_inst/u_spi_ctrl/n243_44 ), .I2(\spiflash_inst/u_spi_ctrl/n263_3 ), .I3(\spiflash_inst/ctrl_cs_r [0]), .F(\spiflash_inst/u_spi_ctrl/n243_33 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s28 .INIT=16'hF077; LUT2 \spiflash_inst/u_spi_ctrl/n243_s29 ( .I0(\spiflash_inst/ctrl_cs_r [2]), .I1(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/u_spi_ctrl/n243_34 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s29 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_ctrl/n243_s30 ( .I0(\spiflash_inst/arb_trans_ctrl [24]), .I1(\spiflash_inst/arb_trans_ctrl [25]), .I2(\spiflash_inst/arb_trans_ctrl [26]), .I3(\spiflash_inst/arb_trans_ctrl [27]), .F(\spiflash_inst/u_spi_ctrl/n243_35 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s30 .INIT=16'h0001; LUT4 \spiflash_inst/u_spi_ctrl/n243_s31 ( .I0(\spiflash_inst/arb_trans_ctrl [24]), .I1(\spiflash_inst/arb_trans_ctrl [27]), .I2(\spiflash_inst/arb_trans_ctrl [26]), .I3(\spiflash_inst/ctrl_cs_r [0]), .F(\spiflash_inst/u_spi_ctrl/n243_36 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s31 .INIT=16'h00EF; LUT4 \spiflash_inst/u_spi_ctrl/n243_s32 ( .I0(\spiflash_inst/arb_trans_ctrl [27]), .I1(\spiflash_inst/u_spi_ctrl/n243_40 ), .I2(\spiflash_inst/arb_trans_ctrl [24]), .I3(\spiflash_inst/u_spi_ctrl/n243_41 ), .F(\spiflash_inst/u_spi_ctrl/n243_37 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s32 .INIT=16'hBF00; LUT4 \spiflash_inst/u_spi_ctrl/n243_s33 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/ctrl_cs_r [0]), .I2(\spiflash_inst/ctrl_cs_r [2]), .I3(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/u_spi_ctrl/n243_38 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s33 .INIT=16'h000E; LUT2 \spiflash_inst/u_spi_ctrl/n244_s31 ( .I0(\spiflash_inst/ctrl_cs_r [0]), .I1(\spiflash_inst/arb_trans_ctrl [29]), .F(\spiflash_inst/u_spi_ctrl/n244_37 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s31 .INIT=4'h4; LUT2 \spiflash_inst/u_spi_ctrl/n244_s32 ( .I0(\spiflash_inst/arb_trans_ctrl [21]), .I1(\spiflash_inst/u_spi_ctrl/n244_46 ), .F(\spiflash_inst/u_spi_ctrl/n244_38 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s32 .INIT=4'h4; LUT3 \spiflash_inst/u_spi_ctrl/n244_s33 ( .I0(\spiflash_inst/u_spi_ctrl/n244_47 ), .I1(\spiflash_inst/u_spi_ctrl/n244_61 ), .I2(\spiflash_inst/u_spi_ctrl/n244_49 ), .F(\spiflash_inst/u_spi_ctrl/n244_39 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s33 .INIT=8'h70; LUT3 \spiflash_inst/u_spi_ctrl/n244_s34 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/u_spi_ctrl/n263_3 ), .I2(\spiflash_inst/ctrl_cs_r [0]), .F(\spiflash_inst/u_spi_ctrl/n244_40 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s34 .INIT=8'h10; LUT4 \spiflash_inst/u_spi_ctrl/n244_s36 ( .I0(\spiflash_inst/arb_trans_ctrl [29]), .I1(\spiflash_inst/arb_trans_ctrl [30]), .I2(\spiflash_inst/u_spi_ctrl/n244_38 ), .I3(\spiflash_inst/n242_33 ), .F(\spiflash_inst/u_spi_ctrl/n244_42 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s36 .INIT=16'h0100; LUT4 \spiflash_inst/u_spi_ctrl/n244_s37 ( .I0(\spiflash_inst/spi_txdata_rd_Z_15 ), .I1(\spiflash_inst/spi_txdata_rd_Z_8 ), .I2(\spiflash_inst/u_spi_ctrl/n244_50 ), .I3(\spiflash_inst/u_spi_ctrl/n244_63 ), .F(\spiflash_inst/u_spi_ctrl/n244_43 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s37 .INIT=16'h1F00; LUT2 \spiflash_inst/u_spi_ctrl/n244_s38 ( .I0(\spiflash_inst/ctrl_cs_r [3]), .I1(\spiflash_inst/ctrl_cs_r [2]), .F(\spiflash_inst/u_spi_ctrl/n244_44 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s38 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_ctrl/n244_s39 ( .I0(\spiflash_inst/n242_33 ), .I1(\spiflash_inst/ctrl_cs_r [1]), .I2(\spiflash_inst/u_spi_ctrl/n244_42 ), .I3(\spiflash_inst/u_spi_ctrl/n244_52 ), .F(\spiflash_inst/u_spi_ctrl/n244_45 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s39 .INIT=16'h0B00; LUT4 \spiflash_inst/u_spi_ctrl/n245_s25 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [0]), .I1(\spiflash_inst/arb_trans_ctrl [9]), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r [1]), .I3(\spiflash_inst/arb_trans_ctrl [10]), .F(\spiflash_inst/u_spi_ctrl/n245_30 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s25 .INIT=16'h9009; LUT4 \spiflash_inst/u_spi_ctrl/n245_s26 ( .I0(\spiflash_inst/u_spi_ctrl/n244_47 ), .I1(\spiflash_inst/u_spi_ctrl/n243_36 ), .I2(\spiflash_inst/u_spi_ctrl/n244_61 ), .I3(\spiflash_inst/u_spi_ctrl/n245_35 ), .F(\spiflash_inst/u_spi_ctrl/n245_31 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s26 .INIT=16'hEF00; LUT4 \spiflash_inst/u_spi_ctrl/n245_s27 ( .I0(\spiflash_inst/spi_txdata_rd_Z_8 ), .I1(\spiflash_inst/spi_txdata_rd_Z_15 ), .I2(\spiflash_inst/u_spi_ctrl/n244_50 ), .I3(\spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_3 ), .F(\spiflash_inst/u_spi_ctrl/n245_32 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s27 .INIT=16'h001F; LUT4 \spiflash_inst/u_spi_ctrl/n245_s28 ( .I0(\spiflash_inst/rx_shift_reg_full_r ), .I1(\spiflash_inst/ctrl_cs_r [1]), .I2(\spiflash_inst/ctrl_cs_r [0]), .I3(\spiflash_inst/u_spi_ctrl/n244_44 ), .F(\spiflash_inst/u_spi_ctrl/n245_33 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s28 .INIT=16'h4F00; LUT4 \spiflash_inst/u_spi_ctrl/n245_s29 ( .I0(\spiflash_inst/u_spi_ctrl/n245_31 ), .I1(\spiflash_inst/u_spi_ctrl/n243_42 ), .I2(\spiflash_inst/u_spi_ctrl/n245_42 ), .I3(\spiflash_inst/u_spi_ctrl/n245_37 ), .F(\spiflash_inst/u_spi_ctrl/n245_34 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s29 .INIT=16'h008F; LUT2 \spiflash_inst/u_spi_ctrl/tx_ready_s7 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [3]), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [4]), .F(\spiflash_inst/u_spi_ctrl/tx_ready_12 ) ); defparam \spiflash_inst/u_spi_ctrl/tx_ready_s7 .INIT=4'h8; LUT4 \spiflash_inst/u_spi_ctrl/tx_ready_s8 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [3]), .I1(\spiflash_inst/arb_addr_len [0]), .I2(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [4]), .I3(\spiflash_inst/arb_addr_len [1]), .F(\spiflash_inst/u_spi_ctrl/tx_ready_13 ) ); defparam \spiflash_inst/u_spi_ctrl/tx_ready_s8 .INIT=16'h9009; LUT4 \spiflash_inst/u_spi_ctrl/tx_ready_s9 ( .I0(\spiflash_inst/ctrl_cs_r [3]), .I1(\spiflash_inst/ctrl_cs_r [1]), .I2(\spiflash_inst/ctrl_cs_r [2]), .I3(\spiflash_inst/ctrl_cs_r [0]), .F(\spiflash_inst/u_spi_ctrl/tx_ready_14 ) ); defparam \spiflash_inst/u_spi_ctrl/tx_ready_s9 .INIT=16'hD3FD; LUT3 \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s7 ( .I0(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [1]), .I1(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .I2(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [0]), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_12 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s7 .INIT=8'h10; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s8 ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [3]), .I1(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .I2(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_15 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_13 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s8 .INIT=16'h00F4; LUT3 \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s9 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_16 ), .I1(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .I2(\spiflash_inst/u_spi_ctrl/n657_3 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_14 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s9 .INIT=8'h0B; LUT2 \spiflash_inst/u_spi_ctrl/n243_s35 ( .I0(\spiflash_inst/arb_trans_ctrl [25]), .I1(\spiflash_inst/arb_trans_ctrl [26]), .F(\spiflash_inst/u_spi_ctrl/n243_40 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s35 .INIT=4'h6; LUT3 \spiflash_inst/u_spi_ctrl/n243_s36 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/ctrl_cs_r [3]), .I2(\spiflash_inst/ctrl_cs_r [0]), .F(\spiflash_inst/u_spi_ctrl/n243_41 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s36 .INIT=8'h10; LUT2 \spiflash_inst/u_spi_ctrl/n243_s37 ( .I0(\spiflash_inst/arb_trans_ctrl [29]), .I1(\spiflash_inst/arb_trans_ctrl [21]), .F(\spiflash_inst/u_spi_ctrl/n243_42 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s37 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_ctrl/n244_s40 ( .I0(\spiflash_inst/arb_trans_ctrl [24]), .I1(\spiflash_inst/arb_trans_ctrl [25]), .I2(\spiflash_inst/arb_trans_ctrl [26]), .I3(\spiflash_inst/arb_trans_ctrl [27]), .F(\spiflash_inst/u_spi_ctrl/n244_46 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s40 .INIT=16'h002B; LUT4 \spiflash_inst/u_spi_ctrl/n244_s41 ( .I0(\spiflash_inst/arb_trans_ctrl [25]), .I1(\spiflash_inst/arb_trans_ctrl [26]), .I2(\spiflash_inst/arb_trans_ctrl [27]), .I3(\spiflash_inst/arb_trans_ctrl [24]), .F(\spiflash_inst/u_spi_ctrl/n244_47 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s41 .INIT=16'h1400; LUT4 \spiflash_inst/u_spi_ctrl/n244_s43 ( .I0(\spiflash_inst/u_spi_ctrl/n244_53 ), .I1(\spiflash_inst/u_spi_ctrl/n244_54 ), .I2(\spiflash_inst/u_spi_ctrl/n244_46 ), .I3(\spiflash_inst/u_spi_ctrl/n243_38 ), .F(\spiflash_inst/u_spi_ctrl/n244_49 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s43 .INIT=16'hEEE0; LUT2 \spiflash_inst/u_spi_ctrl/n244_s44 ( .I0(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [1]), .I1(\spiflash_inst/master_rxdata_wr_lvl_r ), .F(\spiflash_inst/u_spi_ctrl/n244_50 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s44 .INIT=4'h4; LUT2 \spiflash_inst/u_spi_ctrl/n244_s46 ( .I0(\spiflash_inst/ctrl_cs_r [2]), .I1(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/u_spi_ctrl/n244_52 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s46 .INIT=4'h8; LUT4 \spiflash_inst/u_spi_ctrl/n245_s30 ( .I0(\spiflash_inst/u_spi_ctrl/n243_38 ), .I1(\spiflash_inst/arb_trans_ctrl [25]), .I2(\spiflash_inst/u_spi_ctrl/n245_38 ), .I3(\spiflash_inst/u_spi_ctrl/n243_41 ), .F(\spiflash_inst/u_spi_ctrl/n245_35 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s30 .INIT=16'h0CFA; LUT4 \spiflash_inst/u_spi_ctrl/n245_s32 ( .I0(\spiflash_inst/n242_33 ), .I1(\spiflash_inst/ctrl_cs_r [0]), .I2(\spiflash_inst/u_spi_ctrl/n244_52 ), .I3(\spiflash_inst/arb_trans_end_sclk_Z_3 ), .F(\spiflash_inst/u_spi_ctrl/n245_37 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s32 .INIT=16'h004F; LUT3 \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s10 ( .I0(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len [4]), .I2(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [4]), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_15 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s10 .INIT=8'h0D; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s11 ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [4]), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [4]), .I2(\spiflash_inst/u_spi_ctrl/ctrl_word_len [3]), .I3(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_16 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s11 .INIT=16'hB0BB; LUT4 \spiflash_inst/u_spi_ctrl/n244_s47 ( .I0(\spiflash_inst/arb_trans_ctrl [27]), .I1(\spiflash_inst/u_spi_ctrl/n244_55 ), .I2(\spiflash_inst/u_spi_ctrl/n242_31 ), .I3(\spiflash_inst/arb_trans_ctrl [24]), .F(\spiflash_inst/u_spi_ctrl/n244_53 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s47 .INIT=16'h004F; LUT4 \spiflash_inst/u_spi_ctrl/n244_s48 ( .I0(\spiflash_inst/arb_trans_ctrl [27]), .I1(\spiflash_inst/u_spi_ctrl/n243_40 ), .I2(\spiflash_inst/ctrl_cs_r [1]), .I3(\spiflash_inst/ctrl_cs_r [0]), .F(\spiflash_inst/u_spi_ctrl/n244_54 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s48 .INIT=16'hFB0F; LUT4 \spiflash_inst/u_spi_ctrl/n245_s33 ( .I0(\spiflash_inst/arb_trans_ctrl [24]), .I1(\spiflash_inst/arb_trans_ctrl [25]), .I2(\spiflash_inst/arb_trans_ctrl [26]), .I3(\spiflash_inst/arb_trans_ctrl [27]), .F(\spiflash_inst/u_spi_ctrl/n245_38 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s33 .INIT=16'hFCD5; LUT2 \spiflash_inst/u_spi_ctrl/n244_s49 ( .I0(\spiflash_inst/arb_trans_ctrl [25]), .I1(\spiflash_inst/arb_trans_ctrl [26]), .F(\spiflash_inst/u_spi_ctrl/n244_55 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s49 .INIT=4'h4; LUT3 \spiflash_inst/u_spi_ctrl/n852_s5 ( .I0(\spiflash_inst/n242_23 ), .I1(\spiflash_inst/u_spi_ctrl/n243_24 ), .I2(\spiflash_inst/n242_24 ), .F(\spiflash_inst/u_spi_ctrl/n852_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n852_s5 .INIT=8'h01; LUT4 \spiflash_inst/u_spi_ctrl/arb_req_invalid_s4 ( .I0(\spiflash_inst/arb_trans_end_sclk_Z_4 ), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ), .I2(\spiflash_inst/spi_reset_sclk ), .I3(\spiflash_inst/arb_req_sclk ), .F(\spiflash_inst/u_spi_ctrl/arb_req_invalid_10 ) ); defparam \spiflash_inst/u_spi_ctrl/arb_req_invalid_s4 .INIT=16'hF8FF; LUT3 \spiflash_inst/u_spi_ctrl/n243_s38 ( .I0(\spiflash_inst/arb_trans_ctrl [30]), .I1(\spiflash_inst/arb_trans_ctrl [29]), .I2(\spiflash_inst/arb_trans_ctrl [21]), .F(\spiflash_inst/u_spi_ctrl/n243_44 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s38 .INIT=8'h01; LUT4 \spiflash_inst/u_spi_ctrl/n242_s30 ( .I0(\spiflash_inst/arb_trans_ctrl [21]), .I1(\spiflash_inst/u_spi_ctrl/tx_ready_11 ), .I2(\spiflash_inst/ctrl_cs_r [0]), .I3(\spiflash_inst/arb_trans_ctrl [29]), .F(\spiflash_inst/u_spi_ctrl/n242_36 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s30 .INIT=16'h1011; LUT4 \spiflash_inst/u_spi_ctrl/n244_s50 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/u_spi_ctrl/n277_3 ), .I2(\spiflash_inst/u_spi_ctrl/n245_30 ), .I3(\spiflash_inst/ctrl_cs_r [0]), .F(\spiflash_inst/u_spi_ctrl/n244_57 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s50 .INIT=16'hA022; LUT4 \spiflash_inst/u_spi_ctrl/n348_s4 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [6]), .I1(\spiflash_inst/u_spi_ctrl/n351_9 ), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r [4]), .I3(\spiflash_inst/u_spi_ctrl/data_cnt_r [5]), .F(\spiflash_inst/u_spi_ctrl/n348_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n348_s4 .INIT=16'h8000; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s12 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_26 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_13 ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_14 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_18 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s12 .INIT=16'hA800; LUT4 \spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_s3 ( .I0(\spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_3 ), .I1(\spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_4 ), .I2(\spiflash_inst/rxf_full ), .I3(\spiflash_inst/rx_shift_reg_full_r ), .F(\spiflash_inst/spi_rx_hold_Z ) ); defparam \spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_s3 .INIT=16'h9000; LUT4 \spiflash_inst/u_spi_ctrl/n244_s51 ( .I0(\spiflash_inst/u_spi_ctrl/n244_42 ), .I1(\spiflash_inst/ctrl_cs_r [0]), .I2(\spiflash_inst/ctrl_cs_r [1]), .I3(\spiflash_inst/u_spi_ctrl/n243_34 ), .F(\spiflash_inst/u_spi_ctrl/n244_59 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s51 .INIT=16'hFD00; LUT4 \spiflash_inst/u_spi_ctrl/n242_s31 ( .I0(\spiflash_inst/u_spi_ctrl/n242_48 ), .I1(\spiflash_inst/n242_33 ), .I2(\spiflash_inst/ctrl_cs_r [0]), .I3(\spiflash_inst/ctrl_cs_r [1]), .F(\spiflash_inst/u_spi_ctrl/n242_38 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s31 .INIT=16'h0004; LUT4 \spiflash_inst/u_spi_ctrl/n306_s2 ( .I0(\spiflash_inst/spi_cs_r [0]), .I1(\spiflash_inst/spi_cs_r [2]), .I2(\spiflash_inst/spi_cs_r [1]), .I3(\spiflash_inst/arb_trans_end_sclk_Z_4 ), .F(\spiflash_inst/u_spi_ctrl/n306_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n306_s2 .INIT=16'hFEFF; LUT4 \spiflash_inst/u_spi_ctrl/n351_s4 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [2]), .I1(\spiflash_inst/u_spi_ctrl/data_cnt_r [3]), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r [0]), .I3(\spiflash_inst/u_spi_ctrl/data_cnt_r [1]), .F(\spiflash_inst/u_spi_ctrl/n351_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n351_s4 .INIT=16'h8000; LUT4 \spiflash_inst/u_spi_ctrl/n353_s4 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [2]), .I1(\spiflash_inst/u_spi_ctrl/data_cnt_r [0]), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r [1]), .I3(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ), .F(\spiflash_inst/u_spi_ctrl/n353_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n353_s4 .INIT=16'h6A00; LUT4 \spiflash_inst/u_spi_ctrl/n455_s4 ( .I0(\spiflash_inst/u_spi_ctrl/tx_ready_11 ), .I1(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .I2(\spiflash_inst/u_spi_ctrl/n243_25 ), .I3(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_9 ), .F(\spiflash_inst/u_spi_ctrl/n455_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n455_s4 .INIT=16'h2F00; LUT3 \spiflash_inst/u_spi_ctrl/n294_s3 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/n242_23 ), .I2(\spiflash_inst/n242_24 ), .F(\spiflash_inst/u_spi_ctrl/n294_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n294_s3 .INIT=8'h01; LUT3 \spiflash_inst/u_spi_ctrl/n244_s52 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/ctrl_cs_r [2]), .I2(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/u_spi_ctrl/n244_61 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s52 .INIT=8'h02; LUT3 \spiflash_inst/u_spi_ctrl/n488_s4 ( .I0(\spiflash_inst/u_spi_ctrl/n488_7 ), .I1(\spiflash_inst/spi_reset_sclk ), .I2(\spiflash_inst/spi_ns_2_21 ), .F(\spiflash_inst/u_spi_ctrl/n488_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n488_s4 .INIT=8'h02; LUT3 \spiflash_inst/u_spi_ctrl/n489_s4 ( .I0(\spiflash_inst/u_spi_ctrl/n489_7 ), .I1(\spiflash_inst/spi_reset_sclk ), .I2(\spiflash_inst/spi_ns_2_21 ), .F(\spiflash_inst/u_spi_ctrl/n489_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n489_s4 .INIT=8'h02; LUT3 \spiflash_inst/u_spi_ctrl/n702_s5 ( .I0(\spiflash_inst/txf_rd_Z ), .I1(\spiflash_inst/spi_reset_sclk ), .I2(\spiflash_inst/spi_ns_2_21 ), .F(\spiflash_inst/u_spi_ctrl/n702_10 ) ); defparam \spiflash_inst/u_spi_ctrl/n702_s5 .INIT=8'h02; LUT4 \spiflash_inst/u_spi_ctrl/n242_s33 ( .I0(\spiflash_inst/ctrl_cs_r [2]), .I1(\spiflash_inst/ctrl_cs_r [3]), .I2(\spiflash_inst/ctrl_cs_r [0]), .I3(\spiflash_inst/ctrl_cs_r [1]), .F(\spiflash_inst/u_spi_ctrl/n242_42 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s33 .INIT=16'h0400; LUT3 \spiflash_inst/u_spi_ctrl/n245_s34 ( .I0(\spiflash_inst/ctrl_cs_r [0]), .I1(\spiflash_inst/ctrl_cs_r [2]), .I2(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/u_spi_ctrl/n245_40 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s34 .INIT=8'h10; LUT4 \spiflash_inst/u_spi_ctrl/n242_s34 ( .I0(\spiflash_inst/u_spi_ctrl/n242_36 ), .I1(\spiflash_inst/ctrl_cs_r [1]), .I2(\spiflash_inst/ctrl_cs_r [2]), .I3(\spiflash_inst/ctrl_cs_r [3]), .F(\spiflash_inst/u_spi_ctrl/n242_44 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s34 .INIT=16'h0E00; LUT4 \spiflash_inst/u_spi_ctrl/n244_s53 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [0]), .I2(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [1]), .I3(\spiflash_inst/ctrl_cs_r [0]), .F(\spiflash_inst/u_spi_ctrl/n244_63 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s53 .INIT=16'h5400; LUT3 \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_s5 ( .I0(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [1]), .I2(\spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_4 ), .F(\spiflash_inst/rx_bit_cnt_r_4_11 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_s5 .INIT=8'hE1; LUT4 \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s5 ( .I0(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [1]), .I2(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_13 ), .I3(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_9 ), .F(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_11 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s5 .INIT=16'hE0FF; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_s6 ( .I0(\spiflash_inst/u_spi_ctrl/n1002_2 ), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [4]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_26 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_s6 .INIT=16'h3500; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_s7 ( .I0(\spiflash_inst/u_spi_ctrl/n1002_2 ), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [4]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_26 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_s7 .INIT=16'hCA00; LUT4 \spiflash_inst/u_spi_ctrl/n521_s7 ( .I0(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [1]), .I2(\spiflash_inst/spi_reset_sclk ), .I3(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ), .F(\spiflash_inst/u_spi_ctrl/n521_12 ) ); defparam \spiflash_inst/u_spi_ctrl/n521_s7 .INIT=16'h0009; LUT3 \spiflash_inst/u_spi_ctrl/n522_s8 ( .I0(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [0]), .I1(\spiflash_inst/spi_reset_sclk ), .I2(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ), .F(\spiflash_inst/u_spi_ctrl/n522_13 ) ); defparam \spiflash_inst/u_spi_ctrl/n522_s8 .INIT=8'h01; LUT3 \spiflash_inst/u_spi_ctrl/data_cnt_r_8_s7 ( .I0(\spiflash_inst/arb_trans_end_sclk_Z_3 ), .I1(\spiflash_inst/spi_reset_sclk ), .I2(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ), .F(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_8_s7 .INIT=8'h01; LUT3 \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_s5 ( .I0(\spiflash_inst/spi_txdata_rd_Z ), .I1(\spiflash_inst/spi_reset_sclk ), .I2(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ), .F(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_11 ) ); defparam \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_s5 .INIT=8'hFE; LUT4 \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s6 ( .I0(\spiflash_inst/master_rxdata_wr_lvl_r ), .I1(\spiflash_inst/spi_txdata_rd_Z_15 ), .I2(\spiflash_inst/spi_txdata_rd_Z_8 ), .I3(\spiflash_inst/spi_txdata_rd_Z_9 ), .F(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_13 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s6 .INIT=16'h00A8; LUT3 \spiflash_inst/u_spi_ctrl/n245_s35 ( .I0(\spiflash_inst/arb_trans_ctrl [30]), .I1(\spiflash_inst/arb_req_invalid ), .I2(\spiflash_inst/arb_req_sclk ), .F(\spiflash_inst/u_spi_ctrl/n245_42 ) ); defparam \spiflash_inst/u_spi_ctrl/n245_s35 .INIT=8'h10; LUT4 \spiflash_inst/u_spi_ctrl/n243_s39 ( .I0(\spiflash_inst/u_spi_ctrl/n243_44 ), .I1(\spiflash_inst/u_spi_ctrl/n243_28 ), .I2(\spiflash_inst/arb_req_invalid ), .I3(\spiflash_inst/arb_req_sclk ), .F(\spiflash_inst/u_spi_ctrl/n243_46 ) ); defparam \spiflash_inst/u_spi_ctrl/n243_s39 .INIT=16'h0D00; LUT3 \spiflash_inst/u_spi_ctrl/n242_s35 ( .I0(\spiflash_inst/arb_req_invalid ), .I1(\spiflash_inst/arb_req_sclk ), .I2(\spiflash_inst/u_spi_ctrl/n242_48 ), .F(\spiflash_inst/u_spi_ctrl/n242_46 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s35 .INIT=8'h40; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_s6 ( .I0(\spiflash_inst/u_spi_ctrl/n1003_2 ), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_s6 .INIT=16'h0035; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_s6 ( .I0(\spiflash_inst/u_spi_ctrl/n1003_2 ), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_s6 .INIT=16'h3500; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_s6 ( .I0(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .I1(\spiflash_inst/u_spi_ctrl/n1003_2 ), .I2(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]), .I3(\spiflash_inst/spi_lsb ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_s6 .INIT=16'h5044; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_s8 ( .I0(\spiflash_inst/u_spi_ctrl/n1003_2 ), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rx_ptr [2]), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_s8 .INIT=16'hCA00; LUT4 \spiflash_inst/u_spi_ctrl/ctrl_word_len_2_s2 ( .I0(\spiflash_inst/spi_data_len [2]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len_0_6 ), .I2(\spiflash_inst/arb_cs_r [1]), .I3(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len [2]) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_2_s2 .INIT=16'hFFFE; LUT4 \spiflash_inst/u_spi_ctrl/ctrl_word_len_1_s2 ( .I0(\spiflash_inst/spi_data_len [1]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len_0_6 ), .I2(\spiflash_inst/arb_cs_r [1]), .I3(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len [1]) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_1_s2 .INIT=16'hFFFE; LUT4 \spiflash_inst/u_spi_ctrl/ctrl_word_len_0_s4 ( .I0(\spiflash_inst/spi_data_len [0]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len_0_6 ), .I2(\spiflash_inst/arb_cs_r [1]), .I3(\spiflash_inst/arb_cs_r [2]), .F(\spiflash_inst/u_spi_ctrl/ctrl_word_len [0]) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_word_len_0_s4 .INIT=16'hFFFE; LUT4 \spiflash_inst/u_spi_ctrl/n297_s3 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_ctrl/n245_22 ), .I2(\spiflash_inst/u_spi_ctrl/n245_23 ), .I3(\spiflash_inst/u_spi_ctrl/n245_24 ), .F(\spiflash_inst/u_spi_ctrl/n297_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n297_s3 .INIT=16'h0100; LUT4 \spiflash_inst/u_spi_ctrl/n883_s4 ( .I0(\spiflash_inst/txf_rd_data [0]), .I1(\spiflash_inst/txf_rd_data [24]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n883_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n883_s4 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n882_s3 ( .I0(\spiflash_inst/txf_rd_data [1]), .I1(\spiflash_inst/txf_rd_data [25]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n882_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n882_s3 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n881_s3 ( .I0(\spiflash_inst/txf_rd_data [2]), .I1(\spiflash_inst/txf_rd_data [26]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n881_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n881_s3 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n880_s4 ( .I0(\spiflash_inst/txf_rd_data [3]), .I1(\spiflash_inst/txf_rd_data [27]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n880_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n880_s4 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n879_s3 ( .I0(\spiflash_inst/txf_rd_data [4]), .I1(\spiflash_inst/txf_rd_data [28]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n879_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n879_s3 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n878_s4 ( .I0(\spiflash_inst/txf_rd_data [5]), .I1(\spiflash_inst/txf_rd_data [29]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n878_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n878_s4 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n877_s4 ( .I0(\spiflash_inst/txf_rd_data [6]), .I1(\spiflash_inst/txf_rd_data [30]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n877_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n877_s4 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n876_s4 ( .I0(\spiflash_inst/txf_rd_data [7]), .I1(\spiflash_inst/txf_rd_data [31]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n876_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n876_s4 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n875_s3 ( .I0(\spiflash_inst/txf_rd_data [8]), .I1(\spiflash_inst/txf_rd_data [16]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n875_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n875_s3 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n874_s2 ( .I0(\spiflash_inst/txf_rd_data [9]), .I1(\spiflash_inst/txf_rd_data [17]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n874_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n874_s2 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n873_s2 ( .I0(\spiflash_inst/txf_rd_data [10]), .I1(\spiflash_inst/txf_rd_data [18]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n873_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n873_s2 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n872_s3 ( .I0(\spiflash_inst/txf_rd_data [11]), .I1(\spiflash_inst/txf_rd_data [19]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n872_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n872_s3 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n871_s2 ( .I0(\spiflash_inst/txf_rd_data [12]), .I1(\spiflash_inst/txf_rd_data [20]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n871_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n871_s2 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n870_s3 ( .I0(\spiflash_inst/txf_rd_data [13]), .I1(\spiflash_inst/txf_rd_data [21]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n870_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n870_s3 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n869_s3 ( .I0(\spiflash_inst/txf_rd_data [14]), .I1(\spiflash_inst/txf_rd_data [22]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n869_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n869_s3 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n868_s2 ( .I0(\spiflash_inst/txf_rd_data [15]), .I1(\spiflash_inst/txf_rd_data [23]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n868_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n868_s2 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/n867_s3 ( .I0(\spiflash_inst/txf_rd_data [8]), .I1(\spiflash_inst/txf_rd_data [16]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n867_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n867_s3 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n866_s2 ( .I0(\spiflash_inst/txf_rd_data [9]), .I1(\spiflash_inst/txf_rd_data [17]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n866_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n866_s2 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n865_s2 ( .I0(\spiflash_inst/txf_rd_data [10]), .I1(\spiflash_inst/txf_rd_data [18]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n865_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n865_s2 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n864_s3 ( .I0(\spiflash_inst/txf_rd_data [11]), .I1(\spiflash_inst/txf_rd_data [19]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n864_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n864_s3 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n863_s2 ( .I0(\spiflash_inst/txf_rd_data [12]), .I1(\spiflash_inst/txf_rd_data [20]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n863_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n863_s2 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n862_s3 ( .I0(\spiflash_inst/txf_rd_data [13]), .I1(\spiflash_inst/txf_rd_data [21]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n862_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n862_s3 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n861_s3 ( .I0(\spiflash_inst/txf_rd_data [14]), .I1(\spiflash_inst/txf_rd_data [22]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n861_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n861_s3 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n860_s2 ( .I0(\spiflash_inst/txf_rd_data [15]), .I1(\spiflash_inst/txf_rd_data [23]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n860_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n860_s2 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n859_s3 ( .I0(\spiflash_inst/txf_rd_data [0]), .I1(\spiflash_inst/txf_rd_data [24]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n859_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n859_s3 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n858_s2 ( .I0(\spiflash_inst/txf_rd_data [1]), .I1(\spiflash_inst/txf_rd_data [25]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n858_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n858_s2 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n857_s2 ( .I0(\spiflash_inst/txf_rd_data [2]), .I1(\spiflash_inst/txf_rd_data [26]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n857_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n857_s2 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n856_s3 ( .I0(\spiflash_inst/txf_rd_data [3]), .I1(\spiflash_inst/txf_rd_data [27]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n856_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n856_s3 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n855_s2 ( .I0(\spiflash_inst/txf_rd_data [4]), .I1(\spiflash_inst/txf_rd_data [28]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n855_6 ) ); defparam \spiflash_inst/u_spi_ctrl/n855_s2 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n854_s3 ( .I0(\spiflash_inst/txf_rd_data [5]), .I1(\spiflash_inst/txf_rd_data [29]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n854_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n854_s3 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n853_s4 ( .I0(\spiflash_inst/txf_rd_data [6]), .I1(\spiflash_inst/txf_rd_data [30]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n853_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n853_s4 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n852_s6 ( .I0(\spiflash_inst/txf_rd_data [7]), .I1(\spiflash_inst/txf_rd_data [31]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/u_spi_ctrl/n852_11 ) ); defparam \spiflash_inst/u_spi_ctrl/n852_s6 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_0_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [0]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [24]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [0]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_0_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_1_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [1]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [25]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [1]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_1_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_2_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [2]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [26]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [2]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_2_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_3_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [3]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [27]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [3]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_3_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_4_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [4]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [28]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [4]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_4_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_5_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [5]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [29]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [5]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_5_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_6_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [6]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [30]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [6]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_6_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_7_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [7]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [31]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [7]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_7_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_8_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [8]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [16]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [8]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_8_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_9_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [9]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [17]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [9]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_9_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_10_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [10]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [18]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [10]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_10_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_11_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [11]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [19]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [11]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_11_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_12_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [12]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [20]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [12]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_12_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_13_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [13]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [21]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [13]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_13_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_14_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [14]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [22]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [14]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_14_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_15_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [15]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [23]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [15]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_15_s0 .INIT=16'hAAAC; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_16_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [8]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [16]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [16]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_16_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_17_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [9]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [17]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [17]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_17_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_18_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [10]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [18]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [18]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_18_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_19_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [11]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [19]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [19]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_19_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_20_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [12]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [20]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [20]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_20_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_21_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [13]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [21]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [21]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_21_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_22_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [14]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [22]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [22]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_22_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_23_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [15]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [23]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [23]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_23_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_24_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [0]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [24]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [24]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_24_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_25_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [1]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [25]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [25]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_25_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_26_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [2]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [26]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [26]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_26_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_27_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [3]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [27]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [27]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_27_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_28_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [4]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [28]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [28]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_28_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_29_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [5]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [29]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [29]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_29_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_30_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [6]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [30]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [30]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_30_s0 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_s2 ( .I0(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [7]), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [31]), .I2(\spiflash_inst/spi_lsb ), .I3(\spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_4 ), .F(\spiflash_inst/rxf_wr_data_Z [31]) ); defparam \spiflash_inst/u_spi_ctrl/rxf_wr_data_Z_31_s2 .INIT=16'hCCCA; LUT4 \spiflash_inst/u_spi_ctrl/n355_s4 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ), .I2(\spiflash_inst/spi_txdata_rd_Z ), .I3(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_9 ), .F(\spiflash_inst/u_spi_ctrl/n355_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n355_s4 .INIT=16'h4888; LUT3 \spiflash_inst/u_spi_ctrl/data_cnt_r_8_s8 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_13 ), .I1(\spiflash_inst/spi_txdata_rd_Z ), .I2(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_9 ), .F(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_15 ) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_8_s8 .INIT=8'hD5; LUT4 \spiflash_inst/u_spi_ctrl/n1274_s6 ( .I0(\spiflash_inst/rx_shift_reg_full_r ), .I1(\spiflash_inst/spi_reset_sclk ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_18 ), .I3(\spiflash_inst/rxf_full ), .F(\spiflash_inst/u_spi_ctrl/n1274_11 ) ); defparam \spiflash_inst/u_spi_ctrl/n1274_s6 .INIT=16'h3230; LUT4 \spiflash_inst/u_spi_ctrl/n244_s54 ( .I0(\spiflash_inst/u_spi_ctrl/n243_25 ), .I1(\spiflash_inst/u_spi_ctrl/n244_47 ), .I2(\spiflash_inst/u_spi_ctrl/n244_61 ), .I3(\spiflash_inst/u_spi_ctrl/n244_49 ), .F(\spiflash_inst/u_spi_ctrl/n244_65 ) ); defparam \spiflash_inst/u_spi_ctrl/n244_s54 .INIT=16'h2A00; LUT4 \spiflash_inst/u_spi_ctrl/n242_s36 ( .I0(\spiflash_inst/arb_trans_ctrl [30]), .I1(\spiflash_inst/arb_trans_ctrl [29]), .I2(\spiflash_inst/arb_trans_ctrl [21]), .I3(\spiflash_inst/u_spi_ctrl/n242_30 ), .F(\spiflash_inst/u_spi_ctrl/n242_48 ) ); defparam \spiflash_inst/u_spi_ctrl/n242_s36 .INIT=16'h0100; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s16 ( .I0(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [1]), .I2(\spiflash_inst/u_spi_ctrl/spi_rx_hold_Z_4 ), .I3(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_13 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_26 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s16 .INIT=16'h1E00; LUT4 \spiflash_inst/u_spi_ctrl/n561_s4 ( .I0(\spiflash_inst/u_spi_ctrl/n561_7 ), .I1(\spiflash_inst/spi_reset_sclk ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_11 ), .I3(\spiflash_inst/rx_bit_cnt_r_4_11 ), .F(\spiflash_inst/u_spi_ctrl/n561_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n561_s4 .INIT=16'h0002; LUT4 \spiflash_inst/u_spi_ctrl/n564_s4 ( .I0(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [0]), .I1(\spiflash_inst/spi_reset_sclk ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_11 ), .I3(\spiflash_inst/rx_bit_cnt_r_4_11 ), .F(\spiflash_inst/u_spi_ctrl/n564_9 ) ); defparam \spiflash_inst/u_spi_ctrl/n564_s4 .INIT=16'h0001; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_11_s6 ( .I0(\spiflash_inst/rxf_full ), .I1(\spiflash_inst/rx_shift_reg_full_r ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_11_13 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_11_s6 .INIT=16'hF444; LUT3 \spiflash_inst/u_spi_ctrl/n1068_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1076_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1068_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1068_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1069_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1077_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1069_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1069_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1070_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1078_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1070_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1070_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1071_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1079_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1071_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1071_s2 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_s8 ( .I0(\spiflash_inst/rxf_full ), .I1(\spiflash_inst/rx_shift_reg_full_r ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_16 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_s8 .INIT=16'hF444; LUT3 \spiflash_inst/u_spi_ctrl/n1064_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1076_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1064_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1064_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1065_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1077_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1065_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1065_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1066_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1078_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1066_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1066_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1067_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1079_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1067_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1067_s2 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_s8 ( .I0(\spiflash_inst/rxf_full ), .I1(\spiflash_inst/rx_shift_reg_full_r ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_16 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_s8 .INIT=16'hF444; LUT3 \spiflash_inst/u_spi_ctrl/n1060_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1076_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ), .F(\spiflash_inst/u_spi_ctrl/n1060_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1060_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1061_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1077_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ), .F(\spiflash_inst/u_spi_ctrl/n1061_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1061_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1062_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1078_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ), .F(\spiflash_inst/u_spi_ctrl/n1062_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1062_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1063_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1079_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ), .F(\spiflash_inst/u_spi_ctrl/n1063_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1063_s2 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_s8 ( .I0(\spiflash_inst/rxf_full ), .I1(\spiflash_inst/rx_shift_reg_full_r ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_16 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_s8 .INIT=16'hF444; LUT3 \spiflash_inst/u_spi_ctrl/n1056_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1076_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ), .F(\spiflash_inst/u_spi_ctrl/n1056_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1056_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1057_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1077_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ), .F(\spiflash_inst/u_spi_ctrl/n1057_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1057_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1058_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1078_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ), .F(\spiflash_inst/u_spi_ctrl/n1058_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1058_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1059_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1079_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ), .F(\spiflash_inst/u_spi_ctrl/n1059_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1059_s2 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_s8 ( .I0(\spiflash_inst/rxf_full ), .I1(\spiflash_inst/rx_shift_reg_full_r ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_16 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_s8 .INIT=16'hF444; LUT3 \spiflash_inst/u_spi_ctrl/n1052_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1076_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ), .F(\spiflash_inst/u_spi_ctrl/n1052_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1052_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1053_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1077_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ), .F(\spiflash_inst/u_spi_ctrl/n1053_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1053_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1054_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1078_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ), .F(\spiflash_inst/u_spi_ctrl/n1054_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1054_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1055_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1079_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_12 ), .F(\spiflash_inst/u_spi_ctrl/n1055_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1055_s2 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_s10 ( .I0(\spiflash_inst/rxf_full ), .I1(\spiflash_inst/rx_shift_reg_full_r ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_19 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_s10 .INIT=16'hF444; LUT3 \spiflash_inst/u_spi_ctrl/n1048_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1076_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ), .F(\spiflash_inst/u_spi_ctrl/n1048_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1048_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1049_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1077_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ), .F(\spiflash_inst/u_spi_ctrl/n1049_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1049_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1050_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1078_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ), .F(\spiflash_inst/u_spi_ctrl/n1050_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1050_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1051_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1079_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_13 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_15 ), .F(\spiflash_inst/u_spi_ctrl/n1051_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1051_s2 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s6 ( .I0(\spiflash_inst/rxf_full ), .I1(\spiflash_inst/rx_shift_reg_full_r ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_13 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s6 .INIT=16'hF444; LUT3 \spiflash_inst/u_spi_ctrl/n1076_s3 ( .I0(\spiflash_inst/u_spi_ctrl/n1076_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1076_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n1076_s3 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1077_s3 ( .I0(\spiflash_inst/u_spi_ctrl/n1077_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1077_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n1077_s3 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1078_s3 ( .I0(\spiflash_inst/u_spi_ctrl/n1078_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1078_8 ) ); defparam \spiflash_inst/u_spi_ctrl/n1078_s3 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1079_s5 ( .I0(\spiflash_inst/u_spi_ctrl/n1079_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1079_10 ) ); defparam \spiflash_inst/u_spi_ctrl/n1079_s5 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_7_s6 ( .I0(\spiflash_inst/rxf_full ), .I1(\spiflash_inst/rx_shift_reg_full_r ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ), .I3(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_7_13 ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_7_s6 .INIT=16'hF444; LUT3 \spiflash_inst/u_spi_ctrl/n1072_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1076_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1072_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1072_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1073_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1077_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1073_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1073_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1074_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1078_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1074_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1074_s2 .INIT=8'h80; LUT3 \spiflash_inst/u_spi_ctrl/n1075_s2 ( .I0(\spiflash_inst/u_spi_ctrl/n1079_6 ), .I1(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_12 ), .I2(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_12 ), .F(\spiflash_inst/u_spi_ctrl/n1075_7 ) ); defparam \spiflash_inst/u_spi_ctrl/n1075_s2 .INIT=8'h80; LUT4 \spiflash_inst/u_spi_ctrl/n876_s5 ( .I0(\spiflash_inst/n244_24 ), .I1(\spiflash_inst/n242_23 ), .I2(\spiflash_inst/u_spi_ctrl/n243_24 ), .I3(\spiflash_inst/n242_24 ), .F(\spiflash_inst/u_spi_ctrl/n876_10 ) ); defparam \spiflash_inst/u_spi_ctrl/n876_s5 .INIT=16'h0001; DFFCE \spiflash_inst/u_spi_ctrl/ctrl_cs_r_3_s0 ( .D(\spiflash_inst/u_spi_ctrl/n294_8 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/ctrl_cs_r [3]) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_cs_r_3_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/ctrl_cs_r_2_s0 ( .D(\spiflash_inst/u_spi_ctrl/n295_6 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/ctrl_cs_r [2]) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_cs_r_2_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/ctrl_cs_r_1_s0 ( .D(\spiflash_inst/u_spi_ctrl/n296_6 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/ctrl_cs_r [1]) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_cs_r_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/ctrl_cs_r_0_s0 ( .D(\spiflash_inst/u_spi_ctrl/n297_8 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/ctrl_cs_r [0]) ); defparam \spiflash_inst/u_spi_ctrl/ctrl_cs_r_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/arb_busy_sclk_s0 ( .D(\spiflash_inst/u_spi_ctrl/n306_6 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/arb_busy_sclk_Z ) ); defparam \spiflash_inst/u_spi_ctrl/arb_busy_sclk_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_rx_diff_cnt_r_1_s0 ( .D(\spiflash_inst/u_spi_ctrl/n488_9 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_rx_diff_cnt_r [1]) ); defparam \spiflash_inst/u_spi_ctrl/tx_rx_diff_cnt_r_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_rx_diff_cnt_r_0_s0 ( .D(\spiflash_inst/u_spi_ctrl/n489_9 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_rx_diff_cnt_r [0]) ); defparam \spiflash_inst/u_spi_ctrl/tx_rx_diff_cnt_r_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/data_cnt_r_8_s1 ( .D(\spiflash_inst/u_spi_ctrl/n347_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_15 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/data_cnt_r [8]) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_8_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/data_cnt_r_7_s1 ( .D(\spiflash_inst/u_spi_ctrl/n348_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_15 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/data_cnt_r [7]) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_7_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/data_cnt_r_6_s1 ( .D(\spiflash_inst/u_spi_ctrl/n349_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_15 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/data_cnt_r [6]) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_6_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/data_cnt_r_5_s1 ( .D(\spiflash_inst/u_spi_ctrl/n350_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_15 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/data_cnt_r [5]) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_5_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/data_cnt_r_4_s1 ( .D(\spiflash_inst/u_spi_ctrl/n351_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_15 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/data_cnt_r [4]) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_4_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/data_cnt_r_3_s1 ( .D(\spiflash_inst/u_spi_ctrl/n352_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_15 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/data_cnt_r [3]) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_3_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/data_cnt_r_2_s1 ( .D(\spiflash_inst/u_spi_ctrl/n353_9 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_15 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/data_cnt_r [2]) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_2_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/data_cnt_r_1_s1 ( .D(\spiflash_inst/u_spi_ctrl/n354_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/data_cnt_r_8_15 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/data_cnt_r [1]) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_1_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_s1 ( .D(\spiflash_inst/u_spi_ctrl/n451_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_11 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [4]) ); defparam \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_3_s1 ( .D(\spiflash_inst/u_spi_ctrl/n452_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_11 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [3]) ); defparam \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_3_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_2_s1 ( .D(\spiflash_inst/u_spi_ctrl/n453_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_11 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [2]) ); defparam \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_2_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_1_s1 ( .D(\spiflash_inst/u_spi_ctrl/n454_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_11 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [1]) ); defparam \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_1_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_0_s1 ( .D(\spiflash_inst/u_spi_ctrl/n455_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_4_11 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [0]) ); defparam \spiflash_inst/u_spi_ctrl/tx_bit_cnt_r_0_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s1 ( .D(\spiflash_inst/u_spi_ctrl/n521_8 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_11 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [1]) ); defparam \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1 ( .D(\spiflash_inst/u_spi_ctrl/n522_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_11 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_mask_cnt_r [0]) ); defparam \spiflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_s1 ( .D(\spiflash_inst/u_spi_ctrl/n560_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [4]) ); defparam \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_3_s1 ( .D(\spiflash_inst/u_spi_ctrl/n561_9 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]) ); defparam \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_3_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_2_s1 ( .D(\spiflash_inst/u_spi_ctrl/n562_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [2]) ); defparam \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_2_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_1_s1 ( .D(\spiflash_inst/u_spi_ctrl/n563_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [1]) ); defparam \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_1_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_0_s1 ( .D(\spiflash_inst/u_spi_ctrl/n564_9 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_4_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [0]) ); defparam \spiflash_inst/u_spi_ctrl/rx_bit_cnt_r_0_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_ready_s1 ( .D(\spiflash_inst/u_spi_ctrl/n702_10 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_ready_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/tx_ready ) ); defparam \spiflash_inst/u_spi_ctrl/tx_ready_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_31_s1 ( .D(\spiflash_inst/u_spi_ctrl/n852_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [31]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_31_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_30_s1 ( .D(\spiflash_inst/u_spi_ctrl/n853_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [30]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_30_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_29_s1 ( .D(\spiflash_inst/u_spi_ctrl/n854_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [29]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_29_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_28_s1 ( .D(\spiflash_inst/u_spi_ctrl/n855_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [28]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_28_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_27_s1 ( .D(\spiflash_inst/u_spi_ctrl/n856_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [27]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_27_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_26_s1 ( .D(\spiflash_inst/u_spi_ctrl/n857_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [26]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_26_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_25_s1 ( .D(\spiflash_inst/u_spi_ctrl/n858_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [25]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_25_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_24_s1 ( .D(\spiflash_inst/u_spi_ctrl/n859_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [24]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_24_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_23_s1 ( .D(\spiflash_inst/u_spi_ctrl/n860_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [23]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_23_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_22_s1 ( .D(\spiflash_inst/u_spi_ctrl/n861_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [22]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_22_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_21_s1 ( .D(\spiflash_inst/u_spi_ctrl/n862_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [21]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_21_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_20_s1 ( .D(\spiflash_inst/u_spi_ctrl/n863_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [20]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_20_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_19_s1 ( .D(\spiflash_inst/u_spi_ctrl/n864_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [19]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_19_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_18_s1 ( .D(\spiflash_inst/u_spi_ctrl/n865_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [18]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_18_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_17_s1 ( .D(\spiflash_inst/u_spi_ctrl/n866_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [17]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_17_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_16_s1 ( .D(\spiflash_inst/u_spi_ctrl/n867_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [16]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_16_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_15_s1 ( .D(\spiflash_inst/u_spi_ctrl/n868_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [15]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_15_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_14_s1 ( .D(\spiflash_inst/u_spi_ctrl/n869_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [14]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_14_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_13_s1 ( .D(\spiflash_inst/u_spi_ctrl/n870_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [13]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_13_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_12_s1 ( .D(\spiflash_inst/u_spi_ctrl/n871_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [12]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_12_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_11_s1 ( .D(\spiflash_inst/u_spi_ctrl/n872_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [11]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_11_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_10_s1 ( .D(\spiflash_inst/u_spi_ctrl/n873_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [10]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_10_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_9_s1 ( .D(\spiflash_inst/u_spi_ctrl/n874_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [9]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_9_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_8_s1 ( .D(\spiflash_inst/u_spi_ctrl/n875_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [8]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_8_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_7_s1 ( .D(\spiflash_inst/u_spi_ctrl/n876_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [7]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_7_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_6_s1 ( .D(\spiflash_inst/u_spi_ctrl/n877_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [6]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_6_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_5_s1 ( .D(\spiflash_inst/u_spi_ctrl/n878_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [5]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_5_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_4_s1 ( .D(\spiflash_inst/u_spi_ctrl/n879_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [4]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_4_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_3_s1 ( .D(\spiflash_inst/u_spi_ctrl/n880_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [3]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_3_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_2_s1 ( .D(\spiflash_inst/u_spi_ctrl/n881_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [2]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_2_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_1_s1 ( .D(\spiflash_inst/u_spi_ctrl/n882_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [1]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_1_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/tx_mux_r_0_s1 ( .D(\spiflash_inst/u_spi_ctrl/n883_3 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/tx_mux_r_31_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/tx_mux_r [0]) ); defparam \spiflash_inst/u_spi_ctrl/tx_mux_r_0_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1048_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_19 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [31]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_30_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1049_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_19 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [30]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_30_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_29_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1050_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_19 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [29]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_29_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_28_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1051_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_31_19 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [28]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_28_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1052_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [27]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_26_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1053_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [26]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_26_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_25_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1054_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [25]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_25_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_24_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1055_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_27_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [24]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_24_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1056_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [23]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_22_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1057_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [22]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_22_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_21_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1058_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [21]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_21_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_20_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1059_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_23_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [20]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_20_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1060_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [19]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_18_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1061_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [18]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_18_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_17_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1062_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [17]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_17_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_16_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1063_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_19_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [16]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_16_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1064_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [15]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_14_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1065_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [14]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_14_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_13_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1066_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [13]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_13_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_12_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1067_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_15_16 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [12]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_12_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_11_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1068_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_11_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [11]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_11_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_10_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1069_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_11_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [10]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_10_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_9_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1070_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_11_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [9]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_9_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_8_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1071_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_11_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [8]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_8_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_7_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1072_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_7_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [7]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_7_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_6_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1073_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_7_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [6]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_6_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_5_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1074_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_7_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [5]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_5_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_4_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1075_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_7_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [4]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_4_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1076_8 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [3]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1077_8 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [2]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1078_8 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [1]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1 ( .D(\spiflash_inst/u_spi_ctrl/n1079_10 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_13 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/rx_shift_reg_r [0]) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/arb_req_invalid_s1 ( .D(\spiflash_inst/u_spi_ctrl/n21_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_ctrl/arb_req_invalid_10 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/arb_req_invalid ) ); defparam \spiflash_inst/u_spi_ctrl/arb_req_invalid_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/data_cnt_r_0_s3 ( .D(\spiflash_inst/u_spi_ctrl/n355_9 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_ctrl/data_cnt_r [0]) ); defparam \spiflash_inst/u_spi_ctrl/data_cnt_r_0_s3 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s14 ( .D(\spiflash_inst/u_spi_ctrl/n1274_11 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/rx_shift_reg_full_r ) ); defparam \spiflash_inst/u_spi_ctrl/rx_shift_reg_full_r_s14 .INIT=1'b0; ALU \spiflash_inst/u_spi_ctrl/n958_s ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [0]), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [0]), .I3(GND), .CIN(VCC), .COUT(\spiflash_inst/u_spi_ctrl/n958_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n958_2 ) ); defparam \spiflash_inst/u_spi_ctrl/n958_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_ctrl/n957_s ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [1]), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n958_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n957_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n957_2 ) ); defparam \spiflash_inst/u_spi_ctrl/n957_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_ctrl/n956_s ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [2]), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n957_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n956_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n956_2 ) ); defparam \spiflash_inst/u_spi_ctrl/n956_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_ctrl/n955_s ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [3]), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [3]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n956_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n955_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n955_2 ) ); defparam \spiflash_inst/u_spi_ctrl/n955_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_ctrl/n954_s ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [4]), .I1(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [4]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n955_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n954_0_COUT ), .SUM(\spiflash_inst/u_spi_ctrl/n954_2 ) ); defparam \spiflash_inst/u_spi_ctrl/n954_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_ctrl/n1006_s ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [0]), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [0]), .I3(GND), .CIN(VCC), .COUT(\spiflash_inst/u_spi_ctrl/n1006_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n1006_2 ) ); defparam \spiflash_inst/u_spi_ctrl/n1006_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_ctrl/n1005_s ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [1]), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n1006_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n1005_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n1005_2 ) ); defparam \spiflash_inst/u_spi_ctrl/n1005_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_ctrl/n1004_s ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [2]), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n1005_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n1004_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n1004_2 ) ); defparam \spiflash_inst/u_spi_ctrl/n1004_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_ctrl/n1003_s ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [3]), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [3]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n1004_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n1003_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n1003_2 ) ); defparam \spiflash_inst/u_spi_ctrl/n1003_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_ctrl/n1002_s ( .I0(\spiflash_inst/u_spi_ctrl/ctrl_word_len [4]), .I1(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [4]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n1003_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n1002_0_COUT ), .SUM(\spiflash_inst/u_spi_ctrl/n1002_2 ) ); defparam \spiflash_inst/u_spi_ctrl/n1002_s .ALU_MODE=1; ALU \spiflash_inst/u_spi_ctrl/n14_s0 ( .I0(\spiflash_inst/ctrl_cs_r [0]), .I1(\spiflash_inst/n245_21 ), .I3(GND), .CIN(GND), .COUT(\spiflash_inst/u_spi_ctrl/n14_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n14_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n14_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n15_s0 ( .I0(\spiflash_inst/ctrl_cs_r [1]), .I1(\spiflash_inst/n244_24 ), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n14_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n15_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n15_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n15_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n16_s0 ( .I0(\spiflash_inst/ctrl_cs_r [2]), .I1(\spiflash_inst/n243_21 ), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n15_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n16_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n16_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n16_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n17_s0 ( .I0(\spiflash_inst/ctrl_cs_r [3]), .I1(\spiflash_inst/u_spi_ctrl/n242_22 ), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n16_3 ), .COUT(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_clr ), .SUM(\spiflash_inst/u_spi_ctrl/n17_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n17_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n255_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [0]), .I1(\spiflash_inst/arb_trans_ctrl [12]), .I3(GND), .CIN(GND), .COUT(\spiflash_inst/u_spi_ctrl/n255_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n255_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n255_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n256_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [1]), .I1(\spiflash_inst/arb_trans_ctrl [13]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n255_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n256_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n256_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n256_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n257_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [2]), .I1(\spiflash_inst/arb_trans_ctrl [14]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n256_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n257_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n257_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n257_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n258_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [3]), .I1(\spiflash_inst/arb_trans_ctrl [15]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n257_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n258_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n258_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n258_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n259_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [4]), .I1(\spiflash_inst/arb_trans_ctrl [16]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n258_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n259_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n259_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n259_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n260_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [5]), .I1(\spiflash_inst/arb_trans_ctrl [17]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n259_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n260_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n260_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n260_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n261_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [6]), .I1(\spiflash_inst/arb_trans_ctrl [18]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n260_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n261_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n261_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n261_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n262_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [7]), .I1(\spiflash_inst/arb_trans_ctrl [19]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n261_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n262_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n262_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n262_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n263_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [8]), .I1(\spiflash_inst/arb_trans_ctrl [20]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n262_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n263_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n263_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n263_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n269_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [0]), .I1(\spiflash_inst/arb_trans_ctrl [0]), .I3(GND), .CIN(GND), .COUT(\spiflash_inst/u_spi_ctrl/n269_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n269_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n269_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n270_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [1]), .I1(\spiflash_inst/arb_trans_ctrl [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n269_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n270_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n270_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n270_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n271_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [2]), .I1(\spiflash_inst/arb_trans_ctrl [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n270_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n271_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n271_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n271_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n272_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [3]), .I1(\spiflash_inst/arb_trans_ctrl [3]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n271_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n272_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n272_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n272_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n273_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [4]), .I1(\spiflash_inst/arb_trans_ctrl [4]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n272_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n273_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n273_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n273_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n274_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [5]), .I1(\spiflash_inst/arb_trans_ctrl [5]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n273_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n274_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n274_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n274_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n275_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [6]), .I1(\spiflash_inst/arb_trans_ctrl [6]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n274_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n275_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n275_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n275_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n276_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [7]), .I1(\spiflash_inst/arb_trans_ctrl [7]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n275_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n276_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n276_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n276_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n277_s0 ( .I0(\spiflash_inst/u_spi_ctrl/data_cnt_r [8]), .I1(\spiflash_inst/arb_trans_ctrl [8]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n276_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n277_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n277_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n277_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n602_s0 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len [0]), .I3(GND), .CIN(GND), .COUT(\spiflash_inst/u_spi_ctrl/n602_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n602_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n602_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n599_s0 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [1]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n602_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n599_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n599_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n599_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n597_s0 ( .I0(\spiflash_inst/u_spi_ctrl/tx_bit_cnt_r [2]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n599_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n597_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n597_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n597_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n662_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [0]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len [0]), .I3(GND), .CIN(GND), .COUT(\spiflash_inst/u_spi_ctrl/n662_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n662_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n662_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n659_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [1]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n662_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n659_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n659_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n659_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_ctrl/n657_s0 ( .I0(\spiflash_inst/u_spi_ctrl/rx_bit_cnt_r [2]), .I1(\spiflash_inst/u_spi_ctrl/ctrl_word_len [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_ctrl/n659_3 ), .COUT(\spiflash_inst/u_spi_ctrl/n657_3 ), .SUM(\spiflash_inst/u_spi_ctrl/n657_1_SUM ) ); defparam \spiflash_inst/u_spi_ctrl/n657_s0 .ALU_MODE=3; MUX2_LUT5 \spiflash_inst/u_spi_ctrl/n1018_s14 ( .I0(\spiflash_inst/u_spi_ctrl/n1018_10 ), .I1(\spiflash_inst/u_spi_ctrl/n1018_11 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [3]), .O(\spiflash_inst/u_spi_ctrl/n1018_15 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/n1018_s15 ( .I0(\spiflash_inst/u_spi_ctrl/n1018_12 ), .I1(\spiflash_inst/u_spi_ctrl/n1018_13 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [3]), .O(\spiflash_inst/u_spi_ctrl/n1018_17 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/n1022_s14 ( .I0(\spiflash_inst/u_spi_ctrl/n1022_10 ), .I1(\spiflash_inst/u_spi_ctrl/n1022_11 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [3]), .O(\spiflash_inst/u_spi_ctrl/n1022_15 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/n1022_s15 ( .I0(\spiflash_inst/u_spi_ctrl/n1022_12 ), .I1(\spiflash_inst/u_spi_ctrl/n1022_13 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [3]), .O(\spiflash_inst/u_spi_ctrl/n1022_17 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/n1026_s14 ( .I0(\spiflash_inst/u_spi_ctrl/n1026_10 ), .I1(\spiflash_inst/u_spi_ctrl/n1026_11 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [3]), .O(\spiflash_inst/u_spi_ctrl/n1026_15 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/n1026_s15 ( .I0(\spiflash_inst/u_spi_ctrl/n1026_12 ), .I1(\spiflash_inst/u_spi_ctrl/n1026_13 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [3]), .O(\spiflash_inst/u_spi_ctrl/n1026_17 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/n1030_s14 ( .I0(\spiflash_inst/u_spi_ctrl/n1030_10 ), .I1(\spiflash_inst/u_spi_ctrl/n1030_11 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [3]), .O(\spiflash_inst/u_spi_ctrl/n1030_15 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/n1030_s15 ( .I0(\spiflash_inst/u_spi_ctrl/n1030_12 ), .I1(\spiflash_inst/u_spi_ctrl/n1030_13 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [3]), .O(\spiflash_inst/u_spi_ctrl/n1030_17 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s100 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_68 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_69 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [1]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_85 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s101 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_70 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_71 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [1]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_87 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s102 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_72 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_73 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [1]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_89 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s103 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_74 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_75 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [1]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_91 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s104 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_76 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_77 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [1]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_93 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s105 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_78 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_79 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [1]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_95 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s106 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_80 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_81 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [1]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_97 ) ); MUX2_LUT5 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s107 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_82 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_83 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [1]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_99 ) ); MUX2_LUT6 \spiflash_inst/u_spi_ctrl/n1018_s13 ( .I0(\spiflash_inst/u_spi_ctrl/n1018_15 ), .I1(\spiflash_inst/u_spi_ctrl/n1018_17 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [4]), .O(\spiflash_inst/u_spi_ctrl/n1018_19 ) ); MUX2_LUT6 \spiflash_inst/u_spi_ctrl/n1022_s13 ( .I0(\spiflash_inst/u_spi_ctrl/n1022_15 ), .I1(\spiflash_inst/u_spi_ctrl/n1022_17 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [4]), .O(\spiflash_inst/u_spi_ctrl/n1022_19 ) ); MUX2_LUT6 \spiflash_inst/u_spi_ctrl/n1026_s13 ( .I0(\spiflash_inst/u_spi_ctrl/n1026_15 ), .I1(\spiflash_inst/u_spi_ctrl/n1026_17 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [4]), .O(\spiflash_inst/u_spi_ctrl/n1026_19 ) ); MUX2_LUT6 \spiflash_inst/u_spi_ctrl/n1030_s13 ( .I0(\spiflash_inst/u_spi_ctrl/n1030_15 ), .I1(\spiflash_inst/u_spi_ctrl/n1030_17 ), .S0(\spiflash_inst/u_spi_ctrl/rx_ptr [4]), .O(\spiflash_inst/u_spi_ctrl/n1030_19 ) ); MUX2_LUT6 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s96 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_85 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_87 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [2]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_101 ) ); MUX2_LUT6 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s97 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_89 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_91 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [2]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_103 ) ); MUX2_LUT6 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s98 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_93 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_95 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [2]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_105 ) ); MUX2_LUT6 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s99 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_97 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_99 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [2]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_107 ) ); MUX2_LUT7 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s94 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_101 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_103 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [3]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_109 ) ); MUX2_LUT7 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s95 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_105 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_107 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [3]), .O(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_111 ) ); MUX2_LUT8 \spiflash_inst/u_spi_ctrl/sngl_txdata_0_s93 ( .I0(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_109 ), .I1(\spiflash_inst/u_spi_ctrl/sngl_txdata_0_111 ), .S0(\spiflash_inst/u_spi_ctrl/tx_ptr [4]), .O(\spiflash_inst/sngl_txdata [0]) ); LUT3 \spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1 ( .I0(\spiflash_inst/u_spi_spiif/spi_in_d1_r [1]), .I1(\spiflash_inst/u_spi_spiif/spi_in_d1_r [0]), .I2(\spiflash_inst/spi_3line ), .F(\spiflash_inst/u_spi_spiif/n338_2 ) ); defparam \spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s1 .INIT=8'hCA; LUT3 \spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s0 ( .I0(\spiflash_inst/u_spi_spiif/spi_in_r [1]), .I1(\spiflash_inst/u_spi_spiif/spi_in_r [0]), .I2(\spiflash_inst/spi_3line ), .F(\spiflash_inst/u_spi_spiif/n341_2 ) ); defparam \spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s0 .INIT=8'hCA; LUT2 \spiflash_inst/u_spi_spiif/sclk_1t_s0 ( .I0(\spiflash_inst/u_spi_spiif/sclk_1t_4 ), .I1(\spiflash_inst/u_spi_spiif/sclk_1t_5 ), .F(\spiflash_inst/u_spi_spiif/sclk_1t ) ); defparam \spiflash_inst/u_spi_spiif/sclk_1t_s0 .INIT=4'h8; LUT2 \spiflash_inst/u_spi_spiif/master_clk_en_s1 ( .I0(\spiflash_inst/u_spi_spiif/spi_ns [1]), .I1(\spiflash_inst/u_spi_spiif/master_clk_en_5 ), .F(\spiflash_inst/u_spi_spiif/master_clk_en ) ); defparam \spiflash_inst/u_spi_spiif/master_clk_en_s1 .INIT=4'h4; LUT3 \spiflash_inst/u_spi_spiif/O_flash_ck_d_s ( .I0(\spiflash_inst/u_spi_spiif/master_sclk_r ), .I1(\spiflash_inst/u_spi_spiif/O_flash_ck_d_3 ), .I2(\spiflash_inst/spi_mode [1]), .F(O_flash_ck) ); defparam \spiflash_inst/u_spi_spiif/O_flash_ck_d_s .INIT=8'h4B; LUT4 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s ( .I0(\spiflash_inst/u_spi_spiif/spi_ns [2]), .I1(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_3 ), .I2(\spiflash_inst/u_spi_spiif/spi_ns [0]), .I3(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_4 ), .F(\spiflash_inst/spi_txdata_rd_Z ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s .INIT=16'h6000; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_2_s8 ( .I0(\spiflash_inst/u_spi_spiif/spi_ns_2_14 ), .I1(\spiflash_inst/u_spi_spiif/spi_ns_2_25 ), .I2(\spiflash_inst/spi_cs_r [2]), .I3(\spiflash_inst/u_spi_spiif/spi_ns_2_16 ), .F(\spiflash_inst/u_spi_spiif/spi_ns [2]) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s8 .INIT=16'hFE00; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_1_s8 ( .I0(\spiflash_inst/u_spi_spiif/spi_ns_1_14 ), .I1(\spiflash_inst/u_spi_spiif/spi_ns_1_15 ), .I2(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_3 ), .I3(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_4 ), .F(\spiflash_inst/u_spi_spiif/spi_ns [1]) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_1_s8 .INIT=16'hF8FC; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_0_s10 ( .I0(\spiflash_inst/spi_rx_hold_Z ), .I1(\spiflash_inst/u_spi_spiif/spi_ns_0_16 ), .I2(\spiflash_inst/spi_cs_r [0]), .I3(\spiflash_inst/u_spi_spiif/spi_ns_0_17 ), .F(\spiflash_inst/u_spi_spiif/spi_ns [0]) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_0_s10 .INIT=16'hEEE0; LUT3 \spiflash_inst/u_spi_spiif/period_cnt_r_7_s3 ( .I0(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_4 ), .I1(\spiflash_inst/u_spi_spiif/period_cnt_r_7_9 ), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r_7_13 ), .F(\spiflash_inst/u_spi_spiif/period_cnt_r_7_8 ) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_7_s3 .INIT=8'hBF; LUT2 \spiflash_inst/u_spi_spiif/n287_s2 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_spiif/n287_7 ), .F(\spiflash_inst/u_spi_spiif/n287_6 ) ); defparam \spiflash_inst/u_spi_spiif/n287_s2 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_spiif/n263_s2 ( .I0(\spiflash_inst/spi_mode [0]), .I1(\spiflash_inst/u_spi_spiif/spi_ns [0]), .I2(\spiflash_inst/u_spi_spiif/spi_ns [1]), .I3(\spiflash_inst/u_spi_spiif/n263_9 ), .F(\spiflash_inst/u_spi_spiif/n263_6 ) ); defparam \spiflash_inst/u_spi_spiif/n263_s2 .INIT=16'h9000; LUT2 \spiflash_inst/u_spi_spiif/n200_s2 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [0]), .I1(\spiflash_inst/u_spi_spiif/n200_7 ), .F(\spiflash_inst/u_spi_spiif/n200_6 ) ); defparam \spiflash_inst/u_spi_spiif/n200_s2 .INIT=4'h4; LUT3 \spiflash_inst/u_spi_spiif/n199_s2 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [0]), .I1(\spiflash_inst/u_spi_spiif/clock_cnt_r [1]), .I2(\spiflash_inst/u_spi_spiif/n200_7 ), .F(\spiflash_inst/u_spi_spiif/n199_6 ) ); defparam \spiflash_inst/u_spi_spiif/n199_s2 .INIT=8'h60; LUT4 \spiflash_inst/u_spi_spiif/n197_s2 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [2]), .I1(\spiflash_inst/u_spi_spiif/n198_7 ), .I2(\spiflash_inst/u_spi_spiif/clock_cnt_r [3]), .I3(\spiflash_inst/u_spi_spiif/n200_7 ), .F(\spiflash_inst/u_spi_spiif/n197_6 ) ); defparam \spiflash_inst/u_spi_spiif/n197_s2 .INIT=16'h7800; LUT2 \spiflash_inst/u_spi_spiif/n132_s3 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [0]), .I1(\spiflash_inst/u_spi_spiif/n132_10 ), .F(\spiflash_inst/u_spi_spiif/n132_7 ) ); defparam \spiflash_inst/u_spi_spiif/n132_s3 .INIT=4'h4; LUT3 \spiflash_inst/u_spi_spiif/n131_s3 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [1]), .I1(\spiflash_inst/u_spi_spiif/period_cnt_r [0]), .I2(\spiflash_inst/u_spi_spiif/n132_10 ), .F(\spiflash_inst/u_spi_spiif/n131_7 ) ); defparam \spiflash_inst/u_spi_spiif/n131_s3 .INIT=8'h60; LUT4 \spiflash_inst/u_spi_spiif/n129_s3 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [2]), .I1(\spiflash_inst/u_spi_spiif/n130_8 ), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r [3]), .I3(\spiflash_inst/u_spi_spiif/n132_10 ), .F(\spiflash_inst/u_spi_spiif/n129_7 ) ); defparam \spiflash_inst/u_spi_spiif/n129_s3 .INIT=16'h7800; LUT3 \spiflash_inst/u_spi_spiif/n128_s3 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [4]), .I1(\spiflash_inst/u_spi_spiif/n128_10 ), .I2(\spiflash_inst/u_spi_spiif/n132_10 ), .F(\spiflash_inst/u_spi_spiif/n128_7 ) ); defparam \spiflash_inst/u_spi_spiif/n128_s3 .INIT=8'h60; LUT4 \spiflash_inst/u_spi_spiif/n127_s3 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [4]), .I1(\spiflash_inst/u_spi_spiif/n128_10 ), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r [5]), .I3(\spiflash_inst/u_spi_spiif/n132_10 ), .F(\spiflash_inst/u_spi_spiif/n127_7 ) ); defparam \spiflash_inst/u_spi_spiif/n127_s3 .INIT=16'h7800; LUT3 \spiflash_inst/u_spi_spiif/n126_s3 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [6]), .I1(\spiflash_inst/u_spi_spiif/n126_8 ), .I2(\spiflash_inst/u_spi_spiif/n132_10 ), .F(\spiflash_inst/u_spi_spiif/n126_7 ) ); defparam \spiflash_inst/u_spi_spiif/n126_s3 .INIT=8'h60; LUT4 \spiflash_inst/u_spi_spiif/n125_s3 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [6]), .I1(\spiflash_inst/u_spi_spiif/n126_8 ), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r [7]), .I3(\spiflash_inst/u_spi_spiif/n132_10 ), .F(\spiflash_inst/u_spi_spiif/n125_7 ) ); defparam \spiflash_inst/u_spi_spiif/n125_s3 .INIT=16'h7800; LUT2 \spiflash_inst/u_spi_spiif/n79_s2 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_spiif/spi_ns [0]), .F(\spiflash_inst/u_spi_spiif/n79_6 ) ); defparam \spiflash_inst/u_spi_spiif/n79_s2 .INIT=4'h4; LUT2 \spiflash_inst/u_spi_spiif/n78_s2 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_spiif/spi_ns [1]), .F(\spiflash_inst/u_spi_spiif/n78_6 ) ); defparam \spiflash_inst/u_spi_spiif/n78_s2 .INIT=4'h4; LUT2 \spiflash_inst/u_spi_spiif/n77_s2 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_spiif/spi_ns [2]), .F(\spiflash_inst/u_spi_spiif/n77_6 ) ); defparam \spiflash_inst/u_spi_spiif/n77_s2 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_spiif/sclk_1t_s1 ( .I0(\spiflash_inst/reg_spiif_setting [4]), .I1(\spiflash_inst/reg_spiif_setting [5]), .I2(\spiflash_inst/reg_spiif_setting [6]), .I3(\spiflash_inst/reg_spiif_setting [7]), .F(\spiflash_inst/u_spi_spiif/sclk_1t_4 ) ); defparam \spiflash_inst/u_spi_spiif/sclk_1t_s1 .INIT=16'h8000; LUT4 \spiflash_inst/u_spi_spiif/sclk_1t_s2 ( .I0(\spiflash_inst/reg_spiif_setting [0]), .I1(\spiflash_inst/reg_spiif_setting [1]), .I2(\spiflash_inst/reg_spiif_setting [2]), .I3(\spiflash_inst/reg_spiif_setting [3]), .F(\spiflash_inst/u_spi_spiif/sclk_1t_5 ) ); defparam \spiflash_inst/u_spi_spiif/sclk_1t_s2 .INIT=16'h8000; LUT4 \spiflash_inst/u_spi_spiif/master_clk_en_s2 ( .I0(\spiflash_inst/u_spi_spiif/master_clk_en_6 ), .I1(\spiflash_inst/spi_rx_hold_Z ), .I2(\spiflash_inst/u_spi_spiif/spi_ns [2]), .I3(\spiflash_inst/u_spi_spiif/spi_ns [0]), .F(\spiflash_inst/u_spi_spiif/master_clk_en_5 ) ); defparam \spiflash_inst/u_spi_spiif/master_clk_en_s2 .INIT=16'h1000; LUT4 \spiflash_inst/u_spi_spiif/O_flash_ck_d_s0 ( .I0(\spiflash_inst/u_spi_spiif/latch_out_0 ), .I1(\spiflash_inst/u_spi_spiif/latch_out ), .I2(\spiflash_inst/spi_mode [0]), .I3(I_spi_clock), .F(\spiflash_inst/u_spi_spiif/O_flash_ck_d_3 ) ); defparam \spiflash_inst/u_spi_spiif/O_flash_ck_d_s0 .INIT=16'h3FF5; LUT4 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s0 ( .I0(\spiflash_inst/u_spi_spiif/sclk_1t ), .I1(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_5 ), .I2(\spiflash_inst/n306_4 ), .I3(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_6 ), .F(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_3 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s0 .INIT=16'h4F00; LUT3 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s1 ( .I0(\spiflash_inst/spi_txdata_rd_Z_15 ), .I1(\spiflash_inst/spi_txdata_rd_Z_8 ), .I2(\spiflash_inst/spi_txdata_rd_Z_9 ), .F(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_4 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s1 .INIT=8'h0E; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_2_s9 ( .I0(\spiflash_inst/u_spi_spiif/spi_ns_1_14 ), .I1(\spiflash_inst/u_spi_spiif/master_clk_en_6 ), .I2(\spiflash_inst/u_spi_spiif/spi_ns_2_17 ), .I3(\spiflash_inst/u_spi_spiif/sclk_1t ), .F(\spiflash_inst/u_spi_spiif/spi_ns_2_14 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s9 .INIT=16'h1000; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_2_s11 ( .I0(\spiflash_inst/spi_cs_r [0]), .I1(\spiflash_inst/spi_cs_r [1]), .I2(\spiflash_inst/u_spi_spiif/spi_ns_2_20 ), .I3(\spiflash_inst/spi_ns_2_21 ), .F(\spiflash_inst/u_spi_spiif/spi_ns_2_16 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s11 .INIT=16'h007F; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_1_s9 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [1]), .I1(\spiflash_inst/reg_spiif_setting [13]), .I2(\spiflash_inst/u_spi_spiif/spi_ns_1_16 ), .I3(\spiflash_inst/u_spi_spiif/spi_ns_1_17 ), .F(\spiflash_inst/u_spi_spiif/spi_ns_1_14 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_1_s9 .INIT=16'hD400; LUT2 \spiflash_inst/u_spi_spiif/spi_ns_1_s10 ( .I0(\spiflash_inst/spi_cs_r [0]), .I1(\spiflash_inst/spi_cs_r [1]), .F(\spiflash_inst/u_spi_spiif/spi_ns_1_15 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_1_s10 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_0_s11 ( .I0(\spiflash_inst/u_spi_spiif/spi_ns_2_27 ), .I1(\spiflash_inst/u_spi_spiif/spi_ns_0_18 ), .I2(\spiflash_inst/u_spi_spiif/spi_ns_2_18 ), .I3(\spiflash_inst/u_spi_spiif/spi_ns_0_19 ), .F(\spiflash_inst/u_spi_spiif/spi_ns_0_16 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_0_s11 .INIT=16'hB0BB; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_0_s12 ( .I0(\spiflash_inst/u_spi_spiif/master_clk_en_6 ), .I1(\spiflash_inst/u_spi_spiif/spi_ns_2_18 ), .I2(\spiflash_inst/spi_cs_r [1]), .I3(\spiflash_inst/u_spi_spiif/spi_ns_0_20 ), .F(\spiflash_inst/u_spi_spiif/spi_ns_0_17 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_0_s12 .INIT=16'h1F00; LUT3 \spiflash_inst/u_spi_spiif/period_cnt_r_7_s4 ( .I0(\spiflash_inst/u_spi_spiif/sclk_1t_5 ), .I1(\spiflash_inst/u_spi_spiif/sclk_1t_4 ), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r_7_11 ), .F(\spiflash_inst/u_spi_spiif/period_cnt_r_7_9 ) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_7_s4 .INIT=8'h70; LUT2 \spiflash_inst/u_spi_spiif/clock_cnt_r_3_s4 ( .I0(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_5 ), .I1(\spiflash_inst/u_spi_spiif/clock_cnt_r_3_10 ), .F(\spiflash_inst/u_spi_spiif/clock_cnt_r_3_9 ) ); defparam \spiflash_inst/u_spi_spiif/clock_cnt_r_3_s4 .INIT=4'h1; LUT4 \spiflash_inst/u_spi_spiif/n287_s3 ( .I0(\spiflash_inst/spi_cs_r [2]), .I1(\spiflash_inst/spi_cs_r [0]), .I2(\spiflash_inst/u_spi_spiif/sclk_1t ), .I3(\spiflash_inst/spi_cs_r [1]), .F(\spiflash_inst/u_spi_spiif/n287_7 ) ); defparam \spiflash_inst/u_spi_spiif/n287_s3 .INIT=16'hFE7F; LUT4 \spiflash_inst/u_spi_spiif/n200_s3 ( .I0(\spiflash_inst/u_spi_spiif/spi_ns_1_14 ), .I1(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_4 ), .I2(\spiflash_inst/u_spi_spiif/spi_ns_1_15 ), .I3(\spiflash_inst/u_spi_spiif/clock_cnt_r_3_9 ), .F(\spiflash_inst/u_spi_spiif/n200_7 ) ); defparam \spiflash_inst/u_spi_spiif/n200_s3 .INIT=16'hBF00; LUT2 \spiflash_inst/u_spi_spiif/n198_s3 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [0]), .I1(\spiflash_inst/u_spi_spiif/clock_cnt_r [1]), .F(\spiflash_inst/u_spi_spiif/n198_7 ) ); defparam \spiflash_inst/u_spi_spiif/n198_s3 .INIT=4'h8; LUT2 \spiflash_inst/u_spi_spiif/n130_s4 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [1]), .I1(\spiflash_inst/u_spi_spiif/period_cnt_r [0]), .F(\spiflash_inst/u_spi_spiif/n130_8 ) ); defparam \spiflash_inst/u_spi_spiif/n130_s4 .INIT=4'h8; LUT3 \spiflash_inst/u_spi_spiif/n126_s4 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [4]), .I1(\spiflash_inst/u_spi_spiif/period_cnt_r [5]), .I2(\spiflash_inst/u_spi_spiif/n128_10 ), .F(\spiflash_inst/u_spi_spiif/n126_8 ) ); defparam \spiflash_inst/u_spi_spiif/n126_s4 .INIT=8'h80; LUT2 \spiflash_inst/u_spi_spiif/master_clk_en_s3 ( .I0(\spiflash_inst/tx_ready ), .I1(\spiflash_inst/n244_35 ), .F(\spiflash_inst/u_spi_spiif/master_clk_en_6 ) ); defparam \spiflash_inst/u_spi_spiif/master_clk_en_s3 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s2 ( .I0(\spiflash_inst/u_spi_spiif/spi_ns_1_14 ), .I1(\spiflash_inst/u_spi_spiif/master_clk_en_6 ), .I2(\spiflash_inst/u_spi_spiif/spi_ns_2_18 ), .I3(\spiflash_inst/spi_cs_r [0]), .F(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_5 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s2 .INIT=16'h0100; LUT4 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s3 ( .I0(\spiflash_inst/spi_rx_hold_Z ), .I1(\spiflash_inst/u_spi_spiif/spi_ns_0_18 ), .I2(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_10 ), .I3(\spiflash_inst/u_spi_spiif/spi_ns_2_20 ), .F(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_6 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s3 .INIT=16'h0007; LUT4 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s5 ( .I0(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_11 ), .I1(\spiflash_inst/rx_bit_cnt_r_4_11 ), .I2(\spiflash_inst/spi_rx_hold_Z_5 ), .I3(\spiflash_inst/u_spi_spiif/period_cnt_r_7_9 ), .F(\spiflash_inst/spi_txdata_rd_Z_8 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s5 .INIT=16'hDF00; LUT4 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s6 ( .I0(\spiflash_inst/u_spi_spiif/spi_ns_1_14 ), .I1(\spiflash_inst/spi_cs_r [1]), .I2(\spiflash_inst/spi_cs_r [0]), .I3(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_12 ), .F(\spiflash_inst/spi_txdata_rd_Z_9 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s6 .INIT=16'h1C00; LUT2 \spiflash_inst/u_spi_spiif/spi_ns_2_s12 ( .I0(\spiflash_inst/spi_cs_r [1]), .I1(\spiflash_inst/spi_cs_r [0]), .F(\spiflash_inst/u_spi_spiif/spi_ns_2_17 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s12 .INIT=4'h4; LUT3 \spiflash_inst/u_spi_spiif/spi_ns_2_s13 ( .I0(\spiflash_inst/u_spi_spiif/sclk_1t_5 ), .I1(\spiflash_inst/u_spi_spiif/sclk_1t_4 ), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r_7_11 ), .F(\spiflash_inst/u_spi_spiif/spi_ns_2_18 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s13 .INIT=8'h07; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_2_s15 ( .I0(\spiflash_inst/n242_33 ), .I1(\spiflash_inst/arb_trans_end_sclk_Z_3 ), .I2(\spiflash_inst/u_spi_spiif/spi_ns_2_22 ), .I3(\spiflash_inst/spi_cs_r [2]), .F(\spiflash_inst/u_spi_spiif/spi_ns_2_20 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s15 .INIT=16'hB000; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_2_s16 ( .I0(\spiflash_inst/u_spi_spiif/sclk_1t_5 ), .I1(\spiflash_inst/u_spi_spiif/sclk_1t_4 ), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r_7_11 ), .I3(\spiflash_inst/u_spi_spiif/spi_ns_2_23 ), .F(\spiflash_inst/spi_ns_2_21 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s16 .INIT=16'hF800; LUT2 \spiflash_inst/u_spi_spiif/spi_ns_1_s11 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [0]), .I1(\spiflash_inst/reg_spiif_setting [12]), .F(\spiflash_inst/u_spi_spiif/spi_ns_1_16 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_1_s11 .INIT=4'h4; LUT2 \spiflash_inst/u_spi_spiif/spi_ns_1_s12 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [2]), .I1(\spiflash_inst/u_spi_spiif/clock_cnt_r [3]), .F(\spiflash_inst/u_spi_spiif/spi_ns_1_17 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_1_s12 .INIT=4'h1; LUT2 \spiflash_inst/u_spi_spiif/spi_ns_0_s13 ( .I0(\spiflash_inst/spi_cs_r [1]), .I1(\spiflash_inst/spi_cs_r [2]), .F(\spiflash_inst/u_spi_spiif/spi_ns_0_18 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_0_s13 .INIT=4'h4; LUT3 \spiflash_inst/u_spi_spiif/spi_ns_0_s14 ( .I0(\spiflash_inst/spi_cs_r [2]), .I1(\spiflash_inst/spi_cs_r [1]), .I2(\spiflash_inst/spi_cs_r [0]), .F(\spiflash_inst/u_spi_spiif/spi_ns_0_19 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_0_s14 .INIT=8'h40; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_0_s15 ( .I0(\spiflash_inst/n242_33 ), .I1(\spiflash_inst/arb_trans_end_sclk_Z_3 ), .I2(\spiflash_inst/spi_cs_r [2]), .I3(\spiflash_inst/u_spi_spiif/spi_ns_2_22 ), .F(\spiflash_inst/u_spi_spiif/spi_ns_0_20 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_0_s15 .INIT=16'h0B00; LUT3 \spiflash_inst/u_spi_spiif/period_cnt_r_7_s6 ( .I0(\spiflash_inst/reg_spiif_setting [7]), .I1(\spiflash_inst/u_spi_spiif/n149_32 ), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r [7]), .F(\spiflash_inst/u_spi_spiif/period_cnt_r_7_11 ) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_7_s6 .INIT=8'hD4; LUT4 \spiflash_inst/u_spi_spiif/clock_cnt_r_3_s5 ( .I0(\spiflash_inst/spi_ns_2_21 ), .I1(\spiflash_inst/spi_cs_r [1]), .I2(\spiflash_inst/spi_cs_r [2]), .I3(\spiflash_inst/spi_cs_r [0]), .F(\spiflash_inst/u_spi_spiif/clock_cnt_r_3_10 ) ); defparam \spiflash_inst/u_spi_spiif/clock_cnt_r_3_s5 .INIT=16'hFC2F; LUT2 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s7 ( .I0(\spiflash_inst/spi_cs_r [0]), .I1(\spiflash_inst/spi_cs_r [2]), .F(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_10 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s7 .INIT=4'h4; LUT4 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s8 ( .I0(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_13 ), .I1(\spiflash_inst/spi_cs_r [0]), .I2(\spiflash_inst/spi_cs_r [2]), .I3(\spiflash_inst/spi_cs_r [1]), .F(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_11 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s8 .INIT=16'h2C00; LUT3 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s9 ( .I0(\spiflash_inst/tx_ready ), .I1(\spiflash_inst/spi_cs_r [2]), .I2(\spiflash_inst/n244_35 ), .F(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_12 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s9 .INIT=8'h10; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_2_s17 ( .I0(\spiflash_inst/ctrl_cs_r [0]), .I1(\spiflash_inst/ctrl_cs_r [1]), .I2(\spiflash_inst/ctrl_cs_r [3]), .I3(\spiflash_inst/ctrl_cs_r [2]), .F(\spiflash_inst/u_spi_spiif/spi_ns_2_22 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s17 .INIT=16'h01BF; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_2_s18 ( .I0(\spiflash_inst/spi_cs_r [1]), .I1(\spiflash_inst/spi_cs_r [0]), .I2(\spiflash_inst/spi_cs_r [2]), .I3(\spiflash_inst/u_spi_spiif/n215_18 ), .F(\spiflash_inst/u_spi_spiif/spi_ns_2_23 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s18 .INIT=16'h1000; LUT4 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s10 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [0]), .I1(\spiflash_inst/u_spi_spiif/clock_cnt_r [1]), .I2(\spiflash_inst/u_spi_spiif/clock_cnt_r [2]), .I3(\spiflash_inst/u_spi_spiif/clock_cnt_r [3]), .F(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_13 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s10 .INIT=16'h0001; LUT3 \spiflash_inst/u_spi_spiif/clock_cnt_r_3_s6 ( .I0(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_4 ), .I1(\spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_5 ), .I2(\spiflash_inst/u_spi_spiif/clock_cnt_r_3_10 ), .F(\spiflash_inst/u_spi_spiif/clock_cnt_r_3_12 ) ); defparam \spiflash_inst/u_spi_spiif/clock_cnt_r_3_s6 .INIT=8'hFE; LUT4 \spiflash_inst/u_spi_spiif/n198_s4 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [2]), .I1(\spiflash_inst/u_spi_spiif/clock_cnt_r [0]), .I2(\spiflash_inst/u_spi_spiif/clock_cnt_r [1]), .I3(\spiflash_inst/u_spi_spiif/n200_7 ), .F(\spiflash_inst/u_spi_spiif/n198_9 ) ); defparam \spiflash_inst/u_spi_spiif/n198_s4 .INIT=16'h6A00; LUT4 \spiflash_inst/u_spi_spiif/period_cnt_r_7_s7 ( .I0(\spiflash_inst/spi_cs_r [2]), .I1(\spiflash_inst/spi_cs_r [1]), .I2(\spiflash_inst/spi_cs_r [0]), .I3(\spiflash_inst/spi_reset_sclk ), .F(\spiflash_inst/u_spi_spiif/period_cnt_r_7_13 ) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_7_s7 .INIT=16'h00FE; LUT4 \spiflash_inst/u_spi_spiif/n128_s5 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [2]), .I1(\spiflash_inst/u_spi_spiif/period_cnt_r [3]), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r [1]), .I3(\spiflash_inst/u_spi_spiif/period_cnt_r [0]), .F(\spiflash_inst/u_spi_spiif/n128_10 ) ); defparam \spiflash_inst/u_spi_spiif/n128_s5 .INIT=16'h8000; LUT4 \spiflash_inst/u_spi_spiif/n130_s5 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [2]), .I1(\spiflash_inst/u_spi_spiif/period_cnt_r [1]), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r [0]), .I3(\spiflash_inst/u_spi_spiif/n132_10 ), .F(\spiflash_inst/u_spi_spiif/n130_10 ) ); defparam \spiflash_inst/u_spi_spiif/n130_s5 .INIT=16'h6A00; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_2_s19 ( .I0(\spiflash_inst/u_spi_spiif/spi_ns_2_18 ), .I1(\spiflash_inst/u_spi_spiif/spi_ns_2_27 ), .I2(\spiflash_inst/spi_cs_r [0]), .I3(\spiflash_inst/spi_cs_r [1]), .F(\spiflash_inst/u_spi_spiif/spi_ns_2_25 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s19 .INIT=16'h0100; LUT4 \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s11 ( .I0(\spiflash_inst/tx_ready ), .I1(\spiflash_inst/n244_35 ), .I2(\spiflash_inst/spi_rx_hold_Z ), .I3(\spiflash_inst/u_spi_spiif/sclk_1t ), .F(\spiflash_inst/spi_txdata_rd_Z_15 ) ); defparam \spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s11 .INIT=16'h0B00; LUT4 \spiflash_inst/u_spi_spiif/n132_s5 ( .I0(\spiflash_inst/u_spi_spiif/sclk_1t_5 ), .I1(\spiflash_inst/u_spi_spiif/sclk_1t_4 ), .I2(\spiflash_inst/u_spi_spiif/period_cnt_r_7_11 ), .I3(\spiflash_inst/u_spi_spiif/period_cnt_r_7_13 ), .F(\spiflash_inst/u_spi_spiif/n132_10 ) ); defparam \spiflash_inst/u_spi_spiif/n132_s5 .INIT=16'h0700; LUT4 \spiflash_inst/u_spi_spiif/master_rxdata_wr_lvl_r_s4 ( .I0(\spiflash_inst/spi_txdata_rd_Z_15 ), .I1(\spiflash_inst/spi_txdata_rd_Z_8 ), .I2(\spiflash_inst/spi_txdata_rd_Z_9 ), .I3(\spiflash_inst/u_spi_spiif/period_cnt_r_7_13 ), .F(\spiflash_inst/u_spi_spiif/master_rxdata_wr_lvl_r_10 ) ); defparam \spiflash_inst/u_spi_spiif/master_rxdata_wr_lvl_r_s4 .INIT=16'h0EFF; LUT4 \spiflash_inst/u_spi_spiif/n263_s4 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_spiif/sclk_1t_4 ), .I2(\spiflash_inst/u_spi_spiif/sclk_1t_5 ), .I3(\spiflash_inst/u_spi_spiif/spi_ns [2]), .F(\spiflash_inst/u_spi_spiif/n263_9 ) ); defparam \spiflash_inst/u_spi_spiif/n263_s4 .INIT=16'h0015; LUT4 \spiflash_inst/u_spi_spiif/master_sclk_r_s4 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_spiif/n254_2 ), .I2(\spiflash_inst/u_spi_spiif/sclk_1t_4 ), .I3(\spiflash_inst/u_spi_spiif/sclk_1t_5 ), .F(\spiflash_inst/u_spi_spiif/master_sclk_r_10 ) ); defparam \spiflash_inst/u_spi_spiif/master_sclk_r_s4 .INIT=16'hFEEE; LUT3 \spiflash_inst/u_spi_spiif/n331_s1 ( .I0(\spiflash_inst/u_spi_spiif/spi_rx_hold_d_r ), .I1(\spiflash_inst/u_spi_spiif/sclk_1t_4 ), .I2(\spiflash_inst/u_spi_spiif/sclk_1t_5 ), .F(\spiflash_inst/u_spi_spiif/n331_5 ) ); defparam \spiflash_inst/u_spi_spiif/n331_s1 .INIT=8'h40; LUT4 \spiflash_inst/u_spi_spiif/spi_ns_2_s20 ( .I0(\spiflash_inst/arb_req_invalid ), .I1(\spiflash_inst/arb_req_sclk ), .I2(\spiflash_inst/arb_trans_end_sclk_Z_3 ), .I3(\spiflash_inst/u_spi_spiif/spi_ns_2_22 ), .F(\spiflash_inst/u_spi_spiif/spi_ns_2_27 ) ); defparam \spiflash_inst/u_spi_spiif/spi_ns_2_s20 .INIT=16'h4F00; LUT3 \spiflash_inst/u_spi_spiif/n274_s3 ( .I0(\spiflash_inst/spi_reset_sclk ), .I1(\spiflash_inst/u_spi_spiif/spi_ns [0]), .I2(\spiflash_inst/u_spi_spiif/spi_ns [1]), .F(\spiflash_inst/u_spi_spiif/n274_9 ) ); defparam \spiflash_inst/u_spi_spiif/n274_s3 .INIT=8'hAB; DFFCE \spiflash_inst/u_spi_spiif/spi_cs_r_1_s0 ( .D(\spiflash_inst/u_spi_spiif/n78_6 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/spi_cs_r [1]) ); defparam \spiflash_inst/u_spi_spiif/spi_cs_r_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/spi_cs_r_0_s0 ( .D(\spiflash_inst/u_spi_spiif/n79_6 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/spi_cs_r [0]) ); defparam \spiflash_inst/u_spi_spiif/spi_cs_r_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/master_clk_d_en_r_s0 ( .D(\spiflash_inst/u_spi_spiif/master_clk_en ), .CLK(\spiflash_inst/u_spi_spiif/spi_clock_inv_6 ), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/master_clk_d_en_r ) ); defparam \spiflash_inst/u_spi_spiif/master_clk_d_en_r_s0 .INIT=1'b0; DFFPE \spiflash_inst/u_spi_spiif/spi_out_r_0_s0 ( .D(\spiflash_inst/sngl_txdata [0]), .CLK(I_spi_clock), .CE(\spiflash_inst/spi_txdata_rd_Z ), .PRESET(\spiflash_inst/n6_6 ), .Q(IO_flash_di_d) ); defparam \spiflash_inst/u_spi_spiif/spi_out_r_0_s0 .INIT=1'b1; (*gowin_io_reg = "FALSE" *) DFFPE \spiflash_inst/u_spi_spiif/spi_oe_r_1_s0 ( .D(GND), .CLK(I_spi_clock), .CE(\spiflash_inst/spi_txdata_rd_Z ), .PRESET(\spiflash_inst/n6_6 ), .Q(spi_miso_oe) ); defparam \spiflash_inst/u_spi_spiif/spi_oe_r_1_s0 .INIT=1'b1; DFFRE \spiflash_inst/u_spi_spiif/spi_in_r_1_s0 ( .D(IO_flash_do_in), .CLK(O_flash_ck), .CE(VCC), .RESET(GND), .Q(\spiflash_inst/u_spi_spiif/spi_in_r [1]) ); defparam \spiflash_inst/u_spi_spiif/spi_in_r_1_s0 .INIT=1'b0; DFFRE \spiflash_inst/u_spi_spiif/spi_in_r_0_s0 ( .D(IO_flash_di_d), .CLK(O_flash_ck), .CE(VCC), .RESET(GND), .Q(\spiflash_inst/u_spi_spiif/spi_in_r [0]) ); defparam \spiflash_inst/u_spi_spiif/spi_in_r_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/spi_in_d1_r_1_s0 ( .D(\spiflash_inst/u_spi_spiif/spi_in_r [1]), .CLK(\spiflash_inst/u_spi_spiif/spi_clock_inv_6 ), .CE(\spiflash_inst/u_spi_spiif/n331_5 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/spi_in_d1_r [1]) ); defparam \spiflash_inst/u_spi_spiif/spi_in_d1_r_1_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s0 ( .D(\spiflash_inst/u_spi_spiif/spi_in_r [0]), .CLK(\spiflash_inst/u_spi_spiif/spi_clock_inv_6 ), .CE(\spiflash_inst/u_spi_spiif/n331_5 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/spi_in_d1_r [0]) ); defparam \spiflash_inst/u_spi_spiif/spi_in_d1_r_0_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/spi_rx_hold_d_r_s0 ( .D(\spiflash_inst/spi_rx_hold_Z ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/spi_rx_hold_d_r ) ); defparam \spiflash_inst/u_spi_spiif/spi_rx_hold_d_r_s0 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/spi_cs_r_2_s0 ( .D(\spiflash_inst/u_spi_spiif/n77_6 ), .CLK(I_spi_clock), .CE(VCC), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/spi_cs_r [2]) ); defparam \spiflash_inst/u_spi_spiif/spi_cs_r_2_s0 .INIT=1'b0; DFFPE \spiflash_inst/u_spi_spiif/master_cs_r_s0 ( .D(\spiflash_inst/u_spi_spiif/n274_9 ), .CLK(I_spi_clock), .CE(VCC), .PRESET(\spiflash_inst/n6_6 ), .Q(O_flash_cs_n) ); defparam \spiflash_inst/u_spi_spiif/master_cs_r_s0 .INIT=1'b1; DFFCE \spiflash_inst/u_spi_spiif/period_cnt_r_7_s1 ( .D(\spiflash_inst/u_spi_spiif/n125_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/period_cnt_r_7_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/period_cnt_r [7]) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_7_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/period_cnt_r_6_s1 ( .D(\spiflash_inst/u_spi_spiif/n126_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/period_cnt_r_7_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/period_cnt_r [6]) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_6_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/period_cnt_r_5_s1 ( .D(\spiflash_inst/u_spi_spiif/n127_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/period_cnt_r_7_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/period_cnt_r [5]) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_5_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/period_cnt_r_4_s1 ( .D(\spiflash_inst/u_spi_spiif/n128_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/period_cnt_r_7_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/period_cnt_r [4]) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_4_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/period_cnt_r_3_s1 ( .D(\spiflash_inst/u_spi_spiif/n129_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/period_cnt_r_7_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/period_cnt_r [3]) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_3_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/period_cnt_r_2_s1 ( .D(\spiflash_inst/u_spi_spiif/n130_10 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/period_cnt_r_7_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/period_cnt_r [2]) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_2_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/period_cnt_r_1_s1 ( .D(\spiflash_inst/u_spi_spiif/n131_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/period_cnt_r_7_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/period_cnt_r [1]) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_1_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/period_cnt_r_0_s1 ( .D(\spiflash_inst/u_spi_spiif/n132_7 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/period_cnt_r_7_8 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/period_cnt_r [0]) ); defparam \spiflash_inst/u_spi_spiif/period_cnt_r_0_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/clock_cnt_r_3_s1 ( .D(\spiflash_inst/u_spi_spiif/n197_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/clock_cnt_r_3_12 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/clock_cnt_r [3]) ); defparam \spiflash_inst/u_spi_spiif/clock_cnt_r_3_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/clock_cnt_r_2_s1 ( .D(\spiflash_inst/u_spi_spiif/n198_9 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/clock_cnt_r_3_12 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/clock_cnt_r [2]) ); defparam \spiflash_inst/u_spi_spiif/clock_cnt_r_2_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/clock_cnt_r_1_s1 ( .D(\spiflash_inst/u_spi_spiif/n199_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/clock_cnt_r_3_12 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/clock_cnt_r [1]) ); defparam \spiflash_inst/u_spi_spiif/clock_cnt_r_1_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/clock_cnt_r_0_s1 ( .D(\spiflash_inst/u_spi_spiif/n200_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/clock_cnt_r_3_12 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/clock_cnt_r [0]) ); defparam \spiflash_inst/u_spi_spiif/clock_cnt_r_0_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/master_sclk_r_s1 ( .D(\spiflash_inst/u_spi_spiif/n263_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/master_sclk_r_10 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/u_spi_spiif/master_sclk_r ) ); defparam \spiflash_inst/u_spi_spiif/master_sclk_r_s1 .INIT=1'b0; DFFCE \spiflash_inst/u_spi_spiif/master_rxdata_wr_lvl_r_s1 ( .D(\spiflash_inst/u_spi_spiif/n287_6 ), .CLK(I_spi_clock), .CE(\spiflash_inst/u_spi_spiif/master_rxdata_wr_lvl_r_10 ), .CLEAR(\spiflash_inst/n6_6 ), .Q(\spiflash_inst/master_rxdata_wr_lvl_r ) ); defparam \spiflash_inst/u_spi_spiif/master_rxdata_wr_lvl_r_s1 .INIT=1'b0; ALU \spiflash_inst/u_spi_spiif/n149_s16 ( .I0(VCC), .I1(\spiflash_inst/reg_spiif_setting [0]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/period_cnt_r [0]), .COUT(\spiflash_inst/u_spi_spiif/n149_20 ), .SUM(\spiflash_inst/u_spi_spiif/n149_17_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n149_s16 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n149_s17 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [1]), .I1(\spiflash_inst/reg_spiif_setting [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n149_20 ), .COUT(\spiflash_inst/u_spi_spiif/n149_22 ), .SUM(\spiflash_inst/u_spi_spiif/n149_18_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n149_s17 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n149_s18 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [2]), .I1(\spiflash_inst/reg_spiif_setting [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n149_22 ), .COUT(\spiflash_inst/u_spi_spiif/n149_24 ), .SUM(\spiflash_inst/u_spi_spiif/n149_19_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n149_s18 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n149_s19 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [3]), .I1(\spiflash_inst/reg_spiif_setting [3]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n149_24 ), .COUT(\spiflash_inst/u_spi_spiif/n149_26 ), .SUM(\spiflash_inst/u_spi_spiif/n149_20_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n149_s19 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n149_s20 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [4]), .I1(\spiflash_inst/reg_spiif_setting [4]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n149_26 ), .COUT(\spiflash_inst/u_spi_spiif/n149_28 ), .SUM(\spiflash_inst/u_spi_spiif/n149_21_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n149_s20 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n149_s21 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [5]), .I1(\spiflash_inst/reg_spiif_setting [5]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n149_28 ), .COUT(\spiflash_inst/u_spi_spiif/n149_30 ), .SUM(\spiflash_inst/u_spi_spiif/n149_22_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n149_s21 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n149_s22 ( .I0(\spiflash_inst/u_spi_spiif/period_cnt_r [6]), .I1(\spiflash_inst/reg_spiif_setting [6]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n149_30 ), .COUT(\spiflash_inst/u_spi_spiif/n149_32 ), .SUM(\spiflash_inst/u_spi_spiif/n149_23_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n149_s22 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n215_s8 ( .I0(VCC), .I1(\spiflash_inst/reg_spiif_setting [8]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/clock_cnt_r [0]), .COUT(\spiflash_inst/u_spi_spiif/n215_12 ), .SUM(\spiflash_inst/u_spi_spiif/n215_9_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n215_s8 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n215_s9 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [1]), .I1(\spiflash_inst/reg_spiif_setting [9]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n215_12 ), .COUT(\spiflash_inst/u_spi_spiif/n215_14 ), .SUM(\spiflash_inst/u_spi_spiif/n215_10_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n215_s9 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n215_s10 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [2]), .I1(\spiflash_inst/reg_spiif_setting [10]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n215_14 ), .COUT(\spiflash_inst/u_spi_spiif/n215_16 ), .SUM(\spiflash_inst/u_spi_spiif/n215_11_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n215_s10 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n215_s11 ( .I0(\spiflash_inst/u_spi_spiif/clock_cnt_r [3]), .I1(\spiflash_inst/reg_spiif_setting [11]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n215_16 ), .COUT(\spiflash_inst/u_spi_spiif/n215_18 ), .SUM(\spiflash_inst/u_spi_spiif/n215_12_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n215_s11 .ALU_MODE=1; ALU \spiflash_inst/u_spi_spiif/n251_s0 ( .I0(\spiflash_inst/spi_cs_r [0]), .I1(\spiflash_inst/u_spi_spiif/spi_ns [0]), .I3(GND), .CIN(GND), .COUT(\spiflash_inst/u_spi_spiif/n251_3 ), .SUM(\spiflash_inst/u_spi_spiif/n251_1_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n251_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_spiif/n252_s0 ( .I0(\spiflash_inst/spi_cs_r [1]), .I1(\spiflash_inst/u_spi_spiif/spi_ns [1]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n251_3 ), .COUT(\spiflash_inst/u_spi_spiif/n252_3 ), .SUM(\spiflash_inst/u_spi_spiif/n252_1_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n252_s0 .ALU_MODE=3; ALU \spiflash_inst/u_spi_spiif/n253_s0 ( .I0(\spiflash_inst/spi_cs_r [2]), .I1(\spiflash_inst/u_spi_spiif/spi_ns [2]), .I3(GND), .CIN(\spiflash_inst/u_spi_spiif/n252_3 ), .COUT(\spiflash_inst/u_spi_spiif/n254_2 ), .SUM(\spiflash_inst/u_spi_spiif/n253_1_SUM ) ); defparam \spiflash_inst/u_spi_spiif/n253_s0 .ALU_MODE=3; MUX2_LUT5 \spiflash_inst/u_spi_spiif/spi_rxdata_Z_0_s ( .I0(\spiflash_inst/u_spi_spiif/n341_2 ), .I1(\spiflash_inst/u_spi_spiif/n338_2 ), .S0(\spiflash_inst/u_spi_spiif/sclk_1t ), .O(\spiflash_inst/spi_rxdata_Z [0]) ); INV \spiflash_inst/u_spi_spiif/spi_clock_inv_s2 ( .I(I_spi_clock), .O(\spiflash_inst/u_spi_spiif/spi_clock_inv_6 ) ); DLCE \spiflash_inst/u_spi_spiif/master_gclk_0/latch_out_s1 ( .D(\spiflash_inst/u_spi_spiif/master_clk_en ), .G(\spiflash_inst/u_spi_spiif/master_gclk_0/I_spi_clock_d ), .CLEAR(GND), .GE(VCC), .Q(\spiflash_inst/u_spi_spiif/latch_out ) ); defparam \spiflash_inst/u_spi_spiif/master_gclk_0/latch_out_s1 .INIT=1'b0; INV \spiflash_inst/u_spi_spiif/master_gclk_0/I_spi_clock_d_s ( .I(I_spi_clock), .O(\spiflash_inst/u_spi_spiif/master_gclk_0/I_spi_clock_d ) ); DLCE \spiflash_inst/u_spi_spiif/master_gclk_1/latch_out_s0 ( .D(\spiflash_inst/u_spi_spiif/master_clk_d_en_r ), .G(I_spi_clock), .CLEAR(GND), .GE(VCC), .Q(\spiflash_inst/u_spi_spiif/latch_out_0 ) ); defparam \spiflash_inst/u_spi_spiif/master_gclk_1/latch_out_s0 .INIT=1'b0; endmodule