module oc0ta1b_registers ( input clk, input resend, input taken, output waitnull, //wait signal. 1 wait output [23:0] command, output finished ); //------------------------------------------------ `ifdef SIM localparam STARTTIME = 32'd4_000; // 8us localparam WAITTIME = 32'd50_000; //32'd50_000; //1ms `else localparam STARTTIME = 32'd4_000; // 8us localparam WAITTIME = 32'd5_000_000; //32'd5_000_000; //10ms `endif reg [31:0] wait_cnt; reg wait_flag; // Internal signals reg [23:0] sreg; reg finished_temp; reg [8:0] address; // Assign values to outputs assign command = sreg; assign finished = finished_temp; assign waitnull = wait_flag; // When register and value is FFFF // a flag is asserted indicating the configuration is finished always @ (sreg) begin if(sreg == 24'hFFFFFF) begin finished_temp <= 1; end else begin finished_temp <= 0; end end //-------------------------------------------------------- //wait at least 5ms always @ (posedge clk) begin if(resend == 1) wait_cnt <= 32'd0; else if(address == 1) begin if(wait_cnt>=(STARTTIME+WAITTIME)) wait_cnt <= wait_cnt; else wait_cnt <= wait_cnt + 1'b1; end else wait_cnt <= 32'd0; end always @ (posedge clk) begin if(resend == 1) wait_flag <= 1'b0; else if(wait_cnt > STARTTIME && wait_cnt < WAITTIME) wait_flag <= 1'b1; else wait_flag <= 1'b0; end //-------------------------------------------------------- // Get value out of the LUT always @ (posedge clk) begin if(resend == 1) address <= 9'd0;// reset the configuration else if(taken == 1) address <= address+2'd1;// Get the next value case (address) // 0 01 F400X400_240FPS //OC0TAsetting version History // //1. 03/27/2024 V01 // Initial release // based on OC0TA10_EA_00_07_02.ovt // 0: sreg <= 24'h0103_01; 1: sreg <= 24'h0302_31; 2: sreg <= 24'h0304_01; 3: sreg <= 24'h0305_e0; 4: sreg <= 24'h0306_00; 5: sreg <= 24'h0326_d8; 6: sreg <= 24'h3006_0e; 7: sreg <= 24'h300d_08; 8: sreg <= 24'h3018_f0; 9: sreg <= 24'h301c_f0; 10: sreg <= 24'h3020_20; 11: sreg <= 24'h3040_0f; 12: sreg <= 24'h3022_01; 13: sreg <= 24'h3107_40; 14: sreg <= 24'h3216_01; 15: sreg <= 24'h3217_00; 16: sreg <= 24'h3218_c0; `ifndef SIM 17: sreg <= 24'h3219_55; 18: sreg <= 24'h3500_00; 19: sreg <= 24'h3501_01; 20: sreg <= 24'h3502_fe; 21: sreg <= 24'h3506_01; 22: sreg <= 24'h3507_50; 23: sreg <= 24'h3508_01; 24: sreg <= 24'h3509_00; 25: sreg <= 24'h350a_01; 26: sreg <= 24'h350b_00; 27: sreg <= 24'h350c_00; 28: sreg <= 24'h3541_00; 29: sreg <= 24'h3542_40; 30: sreg <= 24'h3605_90; 31: sreg <= 24'h3606_41; 32: sreg <= 24'h3612_00; 33: sreg <= 24'h3620_08; 34: sreg <= 24'h3630_17; 35: sreg <= 24'h3631_99; 36: sreg <= 24'h3639_88; 37: sreg <= 24'h3668_00; 38: sreg <= 24'h3674_00; 39: sreg <= 24'h3677_3f; 40: sreg <= 24'h368f_06; 41: sreg <= 24'h36a2_19; 42: sreg <= 24'h36a4_f1; 43: sreg <= 24'h36a5_2d; 44: sreg <= 24'h3706_30; 45: sreg <= 24'h370d_72; 46: sreg <= 24'h3713_86; 47: sreg <= 24'h3715_03; 48: sreg <= 24'h3716_00; 49: sreg <= 24'h376d_24; 50: sreg <= 24'h3770_3a; 51: sreg <= 24'h3778_00; 52: sreg <= 24'h37a8_03; 53: sreg <= 24'h37a9_00; 54: sreg <= 24'h37df_7d; 55: sreg <= 24'h3800_00; 56: sreg <= 24'h3801_00; 57: sreg <= 24'h3802_00; 58: sreg <= 24'h3803_00; 59: sreg <= 24'h3804_02; 60: sreg <= 24'h3805_8f; 61: sreg <= 24'h3806_01; 62: sreg <= 24'h3807_ef; 63: sreg <= 24'h3808_02; 64: sreg <= 24'h3809_80; 65: sreg <= 24'h380a_01; 66: sreg <= 24'h380b_e0; 67: sreg <= 24'h380c_01; 68: sreg <= 24'h380d_78; 69: sreg <= 24'h380e_02; 70: sreg <= 24'h380f_0c; 71: sreg <= 24'h3810_00; 72: sreg <= 24'h3811_07; 73: sreg <= 24'h3812_00; 74: sreg <= 24'h3813_08; 75: sreg <= 24'h3814_11; 76: sreg <= 24'h3815_11; 77: sreg <= 24'h3816_00; 78: sreg <= 24'h3817_01; 79: sreg <= 24'h3818_00; 80: sreg <= 24'h3819_05; 81: sreg <= 24'h3820_40; 82: sreg <= 24'h3821_04; 83: sreg <= 24'h3823_00; 84: sreg <= 24'h3826_00; 85: sreg <= 24'h3827_00; 86: sreg <= 24'h382b_52; 87: sreg <= 24'h384a_a2; 88: sreg <= 24'h3858_00; 89: sreg <= 24'h3859_00; 90: sreg <= 24'h3860_00; 91: sreg <= 24'h3861_00; 92: sreg <= 24'h3866_0c; 93: sreg <= 24'h3867_07; 94: sreg <= 24'h3884_00; 95: sreg <= 24'h3885_08; 96: sreg <= 24'h3888_50; 97: sreg <= 24'h3893_6c; 98: sreg <= 24'h3898_00; 99: sreg <= 24'h389a_04; 100: sreg <= 24'h389b_01; 101: sreg <= 24'h389c_0b; 102: sreg <= 24'h389d_dc; 103: sreg <= 24'h389f_08; 104: sreg <= 24'h38a0_00; 105: sreg <= 24'h38a1_00; 106: sreg <= 24'h38b1_04; 107: sreg <= 24'h38b2_00; 108: sreg <= 24'h38b3_08; 109: sreg <= 24'h38c1_46; 110: sreg <= 24'h38c9_02; 111: sreg <= 24'h38d4_06; 112: sreg <= 24'h38d5_5a; 113: sreg <= 24'h38d6_08; 114: sreg <= 24'h38d7_3a; 115: sreg <= 24'h391e_00; 116: sreg <= 24'h391f_00; 117: sreg <= 24'h3920_a5; 118: sreg <= 24'h3921_00; 119: sreg <= 24'h3922_00; 120: sreg <= 24'h3923_00; 121: sreg <= 24'h3924_05; 122: sreg <= 24'h3925_00; 123: sreg <= 24'h3926_00; 124: sreg <= 24'h3927_00; 125: sreg <= 24'h3928_1a; 126: sreg <= 24'h3929_01; 127: sreg <= 24'h392a_b4; 128: sreg <= 24'h392b_00; 129: sreg <= 24'h392c_10; 130: sreg <= 24'h392f_40; 131: sreg <= 24'h3a06_06; 132: sreg <= 24'h3a07_78; 133: sreg <= 24'h3a08_08; 134: sreg <= 24'h3a09_80; 135: sreg <= 24'h3a52_00; 136: sreg <= 24'h3a53_01; 137: sreg <= 24'h3a54_0c; 138: sreg <= 24'h3a55_04; 139: sreg <= 24'h3a58_0c; 140: sreg <= 24'h3a59_04; 141: sreg <= 24'h4000_cf; 142: sreg <= 24'h4003_40; 143: sreg <= 24'h4008_04; 144: sreg <= 24'h4009_13; 145: sreg <= 24'h400a_02; 146: sreg <= 24'h400b_34; 147: sreg <= 24'h4010_71; 148: sreg <= 24'h4042_c3; 149: sreg <= 24'h4306_04; 150: sreg <= 24'h4307_12; 151: sreg <= 24'h4500_70; 152: sreg <= 24'h4509_00; 153: sreg <= 24'h450b_83; 154: sreg <= 24'h4604_68; 155: sreg <= 24'h481b_44; 156: sreg <= 24'h481f_30; 157: sreg <= 24'h4823_44; 158: sreg <= 24'h4825_35; 159: sreg <= 24'h4837_11; 160: sreg <= 24'h4f00_04; 161: sreg <= 24'h4f10_04; 162: sreg <= 24'h4f21_01; 163: sreg <= 24'h4f22_00; 164: sreg <= 24'h4f23_54; 165: sreg <= 24'h4f24_51; 166: sreg <= 24'h4f25_41; 167: sreg <= 24'h5000_3f; 168: sreg <= 24'h5001_80; 169: sreg <= 24'h500a_00; 170: sreg <= 24'h5100_00; 171: sreg <= 24'h5111_20; //400x400 //min VTS for 400x400 is 0x1bc 172: sreg <= 24'h3800_00; 173: sreg <= 24'h3801_78; 174: sreg <= 24'h3802_00; 175: sreg <= 24'h3803_28; 176: sreg <= 24'h3804_02; 177: sreg <= 24'h3805_17; 178: sreg <= 24'h3806_01; 179: sreg <= 24'h3807_c7; 180: sreg <= 24'h3808_01; 181: sreg <= 24'h3809_90; 182: sreg <= 24'h380a_01; 183: sreg <= 24'h380b_90; 184: sreg <= 24'h380e_01; 185: sreg <= 24'h380f_bc; 186: sreg <= 24'h3501_01; 187: sreg <= 24'h3502_ae; 188: sreg <= 24'h0100_01; `endif default : sreg <= 24'hFFFF_FF; // End configuration endcase end endmodule