# Makefile for cocotb

# defaults
SIM ?= icarus
TOPLEVEL_LANG ?= verilog

VERILOG_SOURCES ?= $(PWD)/i2c_full_top.v
VERILOG_SOURCES += $(PWD)/../i2c_device_top.v
VERILOG_SOURCES += $(PWD)/../i2c_device.v
VERILOG_SOURCES += $(PWD)/../i2c_serial_interface.v
VERILOG_SOURCES += $(PWD)/../i2c_system_control.v
VERILOG_SOURCES += $(PWD)/../../oc0ta1b/i2c_interface.v
VERILOG_SOURCES += $(PWD)/../../oc0ta1b/oc0ta1b_controller.v
VERILOG_SOURCES += $(PWD)/../../oc0ta1b/oc0ta1b_registers.v
VERILOG_SOURCES += $(PWD)/../../pwm_generator.v
# VERILOG_INCLUDE_DIRS ?= $(PWD)/../

# use VHDL_SOURCES for VHDL files

# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL = full_top

# MODULE is the basename of the Python test file
MODULE = i2c_receiver_tb

# Example of how to add a verilog define
# this is equivalent to `define INSERT_ERROR in the .v file
# COMPILE_ARGS ?= -DINSERT_ERROR 
# and this is how you'd do something like `define NUM_BITS 12
# COMPILE_ARGS ?= -DNUM_BITS=12

COMPILE_ARGS ?= -DSIM

# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim