//////////////////////////////////////////////////////////////////////
//// ////
//// i2c_device.v ////
//// ////
//// This file is part of the i2cDevice opencores effort.
//// ////
//// ////
//// Module Description: ////
//// You will need to modify this file to implement your
//// interface.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// start stop detection states
`ifndef I2C_DEVICE_DEFINES
`define I2C_DEVICE_DEFINES
`define NULL_DET 2'b00
`define START_DET 2'b01
`define STOP_DET 2'b10
`endif
// System clock frequency in MHz
// If you are using a clock frequency below 24MHz, then the macro
// for SDA_DEL_LEN will result in compile errors
// you will need to hand tweak the SDA_DEL_LEN constant definition
//`define CLK_FREQ 24
`define CLK_FREQ 60
// Debounce SCL and SDA over this many clock ticks
// The rise time of SCL and SDA can be up to 1000nS (in standard mode)
// so it is essential to debounce the inputs.
// The spec requires 0.05V of hysteresis, but in practise
// simply debouncing the inputs is sufficient
// I2C spec requires suppresion of spikes of
// maximum duration 50nS, so this debounce time should be greater than 50nS
// Also increases data hold time and decreases data setup time
// during an I2C read operation
// 10 ticks = 208nS @ 48MHz
`define DEB_I2C_LEN (10*`CLK_FREQ)/48
// Delay SCL for use as internal sampling clock
// Using delayed version of SCL to ensure that
// SDA is stable when it is sampled.
// Not entirely citical, as according to I2C spec
// SDA should have a minimum of 100nS of set up time
// with respect to SCL rising edge. But with the very slow edge
// speeds used in I2C it is better to err on the side of caution.
// This delay also has the effect of adding extra hold time to the data
// with respect to SCL falling edge. I2C spec requires 0nS of data hold time.
// 10 ticks = 208nS @ 48MHz
`define SCL_DEL_LEN (10*`CLK_FREQ)/48
// Delay SDA for use in start/stop detection
// Use delayed SDA during start/stop detection to avoid
// incorrect detection at SCL falling edge.
// From I2C spec start/stop setup is 600nS with respect to SCL rising edge
// and start/stop hold is 600nS wrt SCL falling edge.
// So it is relatively easy to discriminate start/stop,
// but data setup time is a minimum of 100nS with respect to SCL rising edge
// and 0nS hold wrt to SCL falling edge.
// So the tricky part is providing robust start/stop detection
// in the presence of regular data transitions.
// This delay time should be less than 100nS
// 4 ticks = 83nS @ 48MHz
`define SDA_DEL_LEN (4*`CLK_FREQ)/48
module i2c_device
#(parameter I2C_ADDRESS = 7'h3C) // 0x3C shifted, equivalent to 0x78 unshifted
(
input clk,
input rst,
input sda_i,
output sda_o,
input scl,
output [7:0] reg_addr, // register address to write or read from in system control
output [7:0] reg_rx_data, // value written by I2C host (need to write to system control)
output reg_wr_en, // write when this is true
input [7:0] reg_tx_data // value currently in system control. should be updated synchronously when reg_addr changes (even if writing)
);
// local wires and regs
reg sdaDeb;
reg sclDeb;
reg [`DEB_I2C_LEN-1:0] sdaPipe;
reg [`DEB_I2C_LEN-1:0] sclPipe;
reg [`SCL_DEL_LEN-1:0] sclDelayed;
reg [`SDA_DEL_LEN-1:0] sdaDelayed;
reg [1:0] startStopDetState;
wire clearStartStopDet;
wire sdaOut;
wire sdaIn;
wire [7:0] regAddr;
wire [7:0] dataToRegIF;
wire writeEn;
wire [7:0] dataFromRegIF;
reg [1:0] rstPipe;
wire rstSyncToClk;
reg startEdgeDet;
assign sda_o = sdaOut;
assign sdaIn = sda_i;
// sync rst rsing edge to clk
always @(posedge clk) begin
if (rst == 1'b1)
rstPipe <= 2'b11;
else
rstPipe <= {rstPipe[0], 1'b0};
end
assign rstSyncToClk = rstPipe[1];
// debounce sda and scl
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
sdaPipe <= {`DEB_I2C_LEN{1'b1}};
sdaDeb <= 1'b1;
sclPipe <= {`DEB_I2C_LEN{1'b1}};
sclDeb <= 1'b1;
end
else begin
sdaPipe <= {sdaPipe[`DEB_I2C_LEN-2:0], sdaIn};
sclPipe <= {sclPipe[`DEB_I2C_LEN-2:0], scl};
if (&sclPipe[`DEB_I2C_LEN-1:1] == 1'b1)
sclDeb <= 1'b1;
else if (|sclPipe[`DEB_I2C_LEN-1:1] == 1'b0)
sclDeb <= 1'b0;
if (&sdaPipe[`DEB_I2C_LEN-1:1] == 1'b1)
sdaDeb <= 1'b1;
else if (|sdaPipe[`DEB_I2C_LEN-1:1] == 1'b0)
sdaDeb <= 1'b0;
end
end
// delay scl and sda
// sclDelayed is used as a delayed sampling clock
// sdaDelayed is only used for start stop detection
// Because sda hold time from scl falling is 0nS
// sda must be delayed with respect to scl to avoid incorrect
// detection of start/stop at scl falling edge.
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
sclDelayed <= {`SCL_DEL_LEN{1'b1}};
sdaDelayed <= {`SDA_DEL_LEN{1'b1}};
end
else begin
sclDelayed <= {sclDelayed[`SCL_DEL_LEN-2:0], sclDeb};
sdaDelayed <= {sdaDelayed[`SDA_DEL_LEN-2:0], sdaDeb};
end
end
// start stop detection
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
startStopDetState <= `NULL_DET;
startEdgeDet <= 1'b0;
end
else begin
if (sclDeb == 1'b1 && sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
startEdgeDet <= 1'b1;
else
startEdgeDet <= 1'b0;
if (clearStartStopDet == 1'b1)
startStopDetState <= `NULL_DET;
else if (sclDeb == 1'b1) begin
if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b1 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b0)
startStopDetState <= `STOP_DET;
else if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
startStopDetState <= `START_DET;
end
end
end
assign dataFromRegIF = reg_tx_data;
assign reg_rx_data = dataToRegIF;
assign reg_addr = regAddr;
assign reg_wr_en = writeEn;
serialInterface #(.I2C_ADDRESS(I2C_ADDRESS))
u_serialInterface (
.clk(clk),
.rst(rstSyncToClk | startEdgeDet),
.dataIn(dataFromRegIF),
.dataOut(dataToRegIF),
.writeEn(writeEn),
.regAddr(regAddr),
.scl(sclDelayed[`SCL_DEL_LEN-1]),
.sdaIn(sdaDeb),
.sdaOut(sdaOut),
.startStopDetState(startStopDetState),
.clearStartStopDet(clearStartStopDet)
);
endmodule