<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
    <Version>beta</Version>
    <Device id="GW5A-25B" package="MBGA121N" speed="1" partNumber="GW5A-LV25MG121NC1/I0"/>
    <FileList>
        <File path="C:/Users/david/Documents/GitHub/bs2_eyetracking/src/fifo_top/temp/FIFO/fifo_define.v" type="verilog"/>
        <File path="C:/Users/david/Documents/GitHub/bs2_eyetracking/src/fifo_top/temp/FIFO/fifo_parameter.v" type="verilog"/>
        <File path="C:/Gowin/Gowin_V1.9.11.03_x64/IDE/ipcore/FIFO/data/edc.v" type="verilog"/>
        <File path="C:/Gowin/Gowin_V1.9.11.03_x64/IDE/ipcore/FIFO/data/fifo.v" type="verilog"/>
        <File path="C:/Gowin/Gowin_V1.9.11.03_x64/IDE/ipcore/FIFO/data/fifo_top.v" type="verilog"/>
    </FileList>
    <OptionList>
        <Option type="disable_insert_pad" value="1"/>
        <Option type="include_path" value="C:/Users/david/Documents/GitHub/bs2_eyetracking/src/fifo_top/temp/FIFO"/>
        <Option type="output_file" value="fifo_top.vg"/>
        <Option type="output_template" value="fifo_top_tmp.v"/>
        <Option type="ram_balance" value="1"/>
        <Option type="ram_rw_check" value="1"/>
        <Option type="vcc" value="0.9"/>
        <Option type="vccx" value="3.3"/>
        <Option type="verilog_language" value="sysv-2017"/>
    </OptionList>
</Project>
