<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW5A-25B" pn="GW5A-LV25MG121NC1/I0">gw5a25b-003</Device>
    <FileList>
        <File path="src/MIPI_CSI_HardPhy_Rx.v" type="file.verilog" enable="1"/>
        <File path="src/MIPI_CSI_SoftPhy_MyRx.v" type="file.verilog" enable="1"/>
        <File path="src/MIPI_CSI_SoftPhy_Rx.v" type="file.verilog" enable="0"/>
        <File path="src/adcreq.v" type="file.verilog" enable="1"/>
        <File path="src/adctrig.v" type="file.verilog" enable="1"/>
        <File path="src/big_ila_monitor.v" type="file.verilog" enable="1"/>
        <File path="src/big_ila_top.v" type="file.verilog" enable="1"/>
        <File path="src/big_ila_usb_rec.v" type="file.verilog" enable="1"/>
        <File path="src/big_ila_usb_xmit.v" type="file.verilog" enable="1"/>
        <File path="src/core-usb-dfu/dfu_defs.v" type="file.verilog" enable="0"/>
        <File path="src/core-usb-dfu/fifo_top/spi_read_fifo_2048.v" type="file.verilog" enable="0"/>
        <File path="src/core-usb-dfu/fifo_top/spi_write_fifo_2048.v" type="file.verilog" enable="0"/>
        <File path="src/core-usb-dfu/nak_interceptor.v" type="file.verilog" enable="0"/>
        <File path="src/core-usb-dfu/spi_flash_interface/spi_flash_interface.v" type="file.verilog" enable="0"/>
        <File path="src/core-usb-dfu/spifs_intf.v" type="file.verilog" enable="0"/>
        <File path="src/core-usb-dfu/usb_control_handler_dfu.v" type="file.verilog" enable="0"/>
        <File path="src/core-usb-dfu/usb_descriptor_dfu.v" type="file.verilog" enable="0"/>
        <File path="src/core-usb-dfu/usb_to_spifs.v" type="file.verilog" enable="0"/>
        <File path="src/core_jpeg_encoder/gowin_mult/mult_apdxb.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/gowin_mult/mult_axb.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/gowin_mult/mult_axbmc.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/huff_fifo_sc_afull/huff_fifo_sc_afull.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/img_fifo.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/img_fifo_fwft.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/img_fifo_fwft_adapter.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_combine_huff_coeff.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_dct8x8_nozigzag.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_dct_aan.v" type="file.verilog" enable="0"/>
        <File path="src/core_jpeg_encoder/jpeg_dct_aan_ip.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_ff_stuffer.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_huff_top_color.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_hufftab_ac.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_hufftab_dc.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_preamble_mux_color.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_quantizer.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_rle_color.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_shift_reg_new.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/jpeg_top_color.v" type="file.verilog" enable="1"/>
        <File path="src/core_jpeg_encoder/shiftreg_fifo_sc/shiftreg_fifo_sc.v" type="file.verilog" enable="1"/>
        <File path="src/current_monitor.v" type="file.verilog" enable="1"/>
        <File path="src/fifo_top/fifo_top.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_adc/gowin_adc.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_mipi_dphy/gowin_mipi_dphy.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_pll/gowin_pll.v" type="file.verilog" enable="0"/>
        <File path="src/gowin_pll_191103/gowin_pll.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_pll_191103/gowin_pll_mod.v" type="file.verilog" enable="1"/>
        <File path="src/i2c_receiver/i2c_device.v" type="file.verilog" enable="1"/>
        <File path="src/i2c_receiver/i2c_device_top.v" type="file.verilog" enable="1"/>
        <File path="src/i2c_receiver/i2c_serial_interface.v" type="file.verilog" enable="1"/>
        <File path="src/i2c_receiver/i2c_system_control.v" type="file.verilog" enable="1"/>
        <File path="src/irled_pulse.v" type="file.verilog" enable="1"/>
        <File path="src/isoc_video_buffer/isoc_video_buffer.v" type="file.verilog" enable="1"/>
        <File path="src/isoc_video_buffer/isoc_video_buffer_rx.v" type="file.verilog" enable="1"/>
        <File path="src/isoc_video_buffer/isoc_video_buffer_tx.v" type="file.verilog" enable="1"/>
        <File path="src/line_combiner.v" type="file.verilog" enable="1"/>
        <File path="src/mipi_byte_to_pixel_converter/mipi_byte_to_pixel_converter.v" type="file.verilog" enable="0"/>
        <File path="src/mipi_byte_to_pixel_converter_v191103/mipi_byte_to_pixel_converter.v" type="file.verilog" enable="1"/>
        <File path="src/mipi_csi2_rx/mipi_csi2_rx.v" type="file.verilog" enable="0"/>
        <File path="src/mipi_dsi_csi2_rx/mipi_dsi_csi2_rx.v" type="file.verilog" enable="1"/>
        <File path="src/mipi_pixel_pll/mipi_pixel_pll_60MHz.v" type="file.verilog" enable="0"/>
        <File path="src/mipi_pixel_pll_191103/mipi_pixel_pll_60MHz.v" type="file.verilog" enable="1"/>
        <File path="src/mipi_pixel_pll_191103/mipi_pixel_pll_60MHz_mod.v" type="file.verilog" enable="1"/>
        <File path="src/oc0ta1b/i2c_interface.v" type="file.verilog" enable="1"/>
        <File path="src/oc0ta1b/oc0ta1b_controller.v" type="file.verilog" enable="1"/>
        <File path="src/oc0ta1b/oc0ta1b_registers_24MHz.v" type="file.verilog" enable="1"/>
        <File path="src/pll_init.v" type="file.verilog" enable="1"/>
        <File path="src/pwm_generator.v" type="file.verilog" enable="0"/>
        <File path="src/sw_ver.v" type="file.verilog" enable="0"/>
        <File path="src/top.v" type="file.verilog" enable="1"/>
        <File path="src/usb2_0_softphy/usb2_0_softphy.v" type="file.verilog" enable="0"/>
        <File path="src/usb2_0_softphy_191003/usb2_0_softphy_191003.v" type="file.verilog" enable="1"/>
        <File path="src/usb_control_handler.v" type="file.verilog" enable="1"/>
        <File path="src/usb_device_controller/usb_device_controller.v" type="file.verilog" enable="1"/>
        <File path="src/usb_video/usb_defs.v" type="file.verilog" enable="0"/>
        <File path="src/usb_video/usb_descriptor_video_mjpeg.v" type="file.verilog" enable="1"/>
        <File path="src/usb_video/usb_descriptor_video_mjpeg_bi.v" type="file.verilog" enable="0"/>
        <File path="src/usb_video/uvc_defs.v" type="file.verilog" enable="0"/>
        <File path="src/vid_buf_fifo/vid_buf_fifo.v" type="file.verilog" enable="1"/>
        <File path="src/vid_buf_fifo_a/vid_buf_fifo_a.v" type="file.verilog" enable="0"/>
        <File path="src/vidgen_diag.v" type="file.verilog" enable="0"/>
        <File path="src/bs2-USB-Video-Class.cst" type="file.cst" enable="0"/>
        <File path="src/bs2_eyetracking.cst" type="file.cst" enable="1"/>
        <File path="src/bs2-USB-Video-Class.sdc" type="file.sdc" enable="1"/>
        <File path="src/bs2-USB-Video-Class.rao" type="file.gao" enable="0"/>
    </FileList>
</Project>
