# VXR7200 Display SoC

The **Synaptics VXR7200** is the display system-on-chip that bridges DisplayPort 1.4 input to dual MIPI DSI output for the two OLED panels. The MCU controls it via an I2C-based "Remote Control" (RC) debug register interface.

## Remote Control Interface

**I2C address:** `0x72` (unshifted 7-bit)

All interactions go through a set of debug registers:

| Register | Address | Purpose |
|----------|---------|---------|
| RC_TRIGGER | `0x002000FC` | Write `0xF2` to trigger a command |
| RC_COMMAND | `0x00200110` | Command word (bitfield) |
| RC_OFFSET | `0x00200114` | Target address for read/write operations |
| RC_LENGTH | `0x00200118` | Data length |
| RC_DATA0–DATA7 | `0x00200120`–`0x0020013C` | Up to 32 bytes of data (8 x 32-bit words) |

### Command Word Bitfield

```
[22:16] = Command code
[23]    = Active flag (1 = command in progress)
[31:24] = Result code (0 = success)
```

### Available RC Commands

| Command | Code | Description |
|---------|------|-------------|
| Enable_RC | 0x01 | Enable remote control interface |
| Disable_RC | 0x02 | Disable remote control interface |
| Write_Flash | 0x20 | Program VXR SPI flash |
| Erase_Flash | 0x14 | Erase VXR SPI flash sector |
| Send_Flash_Cmd | 0x25 | Send raw SPI flash command |
| Read_SPI_Flash | 0x30 | Read from VXR SPI flash |
| Get_FW_Chksum | 0x11 | Compute firmware checksum |
| Memory_Write | 0x21 | Write to VXR internal memory |
| Memory_Read | 0x31 | Read from VXR internal memory |
| MIPI_Write | 0x70 | Send MIPI DSI write to display |
| MIPI_Write_Buffered | 0x71 | Buffered MIPI DSI write |
| I2C_Write | 0x72 | I2C passthrough write |
| MIPI_Read | 0x73 | Send MIPI DSI read from display |
| MIPI_Read_From_Buffer | 0x74 | Read buffered MIPI response |
| I2C_Read | 0x75 | I2C passthrough read |

### Timeouts

| Operation | Timeout | Duration |
|-----------|---------|----------|
| Default | 50 RTT ticks | ~5 ms |
| Programming | 150 RTT ticks | ~15 ms |
| MIPI Read | 500 RTT ticks | ~50 ms |
| Flash Erase | 5000 RTT ticks | ~500 ms |

### Error Codes

| Code | Name |
|------|------|
| 0 | RC_Success |
| 1 | RC_Invalid_Arg |
| 2 | RC_Unsupported |
| 3 | RC_Unknown_Error |
| 4 | RC_Iface_Disabled |
| 5 | RC_Bus_Error |
| 6 | RC_Timeout_Error |

## VXR7200 Flash Memory Layout

The VXR7200 has a 512 KB SPI flash with dual config and dual firmware banks:

```
0x00000 ┌──────────────────────┐
        │  Config 0 (32 KB)    │
0x07FF0 │  Config 0 Tag        │
0x08000 ├──────────────────────┤
        │  Firmware 0 (96 KB)  │
0x1FFF0 │  Firmware 0 Tag      │
0x20000 ├──────────────────────┤
        │  Config 1 (32 KB)    │
0x27FF0 │  Config 1 Tag        │
0x28000 ├──────────────────────┤
        │  Firmware 1 (96 KB)  │
0x3FFF0 │  Firmware 1 Tag      │
0x40000 └──────────────────────┘
```

Each bank has a 16-byte tag region at the end that indicates validity. The `VXR_TAGS` HID command (`T`) returns a bitfield showing which banks are active.

## Firmware Management via HID

### Programming Flow

1. **Delete** target bank with `VXR_DELETE` (`D`) — requires "VXRDELETE" safety phrase
   - 64 KB block erase (banks 0–7) or 4 KB sector erase (sectors 0–127)
2. **Program** in 32-byte chunks with `VXR_PROGRAM` (`A`)
3. **Verify** with `VXR_CHECKSUM` (`K`) — computes checksum over specified address range
4. **Reset** VXR7200 with `VXR_RESET` (`Y`) to boot new firmware

### Other VXR HID Commands

- `VXR_FWNAME` (`N`): Returns 15-byte firmware name/version string
- `VXR_TAGS` (`T`): Returns active bank bitfield

## VXR Power Control (BS2)

On BS2 boards, the VXR7200 can be power-gated:

- **Power down:** Disable 1.0V rail via `VIDEOPROC_VXR_POWER_DOWN` notification
- **Power up:** Enable 1.0V rail, wait 275 ms for reset, then access RC interface. I2C peripheral resets on transaction error to recover from stale bus state (v0.3.15). No longer probes VXR when powered down (v0.3.15).
- **Auto-shutdown:** When VXR sleep is enabled (config tag `0x0F`), the VXR7200 powers down after 30 seconds without video input. Tundra UART activity from the tracker wakes it back up; if no video arrives within 30 seconds, it powers down again. Default is no sleep (v0.3.18).
- **HID control:** Dedicated HID commands to manually disable/enable the VXR 1.0V rail (v0.3.15)

### VXR Status in Telemetry (v0.3.15-a)

An extra byte (byte 26) is appended to the periodic telemetry report (length byte unchanged for backward compatibility):
- **Bit 0:** VXR powered down (1 = off, 0 = on)
- **Bit 1:** VXR startup succeeded (1 = success, 0 = failed or not yet)

The 1.8V rail is always on for BS2 (unlike BS1 where it can be individually controlled).

## Key VXR Registers Read by MCU

| Register | Address | Purpose |
|----------|---------|---------|
| RX_LINK_RATE | `0x1880` | DP link rate + lane count |
| EDID_RAM | `0x3000` | Main EDID data |
| EDID_TX0_RAM | `0x3200` | MST left eye EDID |
| EDID_TX1_RAM | `0x3380` | MST right eye EDID |
| TX0_PPS | `0x0780` | DSC PPS for left eye |
| TX1_PPS | `0x0800` | DSC PPS for right eye |
| TX0_VID_MODE | `0x310040` | Left eye video enable status |
| TX1_VID_MODE | `0x350040` | Right eye video enable status |
| RX_FRM0_MSA_TOTALS | `0x220830` | H/V totals for TX0 |
| RX_FRM0_MSA_ACTIVE | `0x220838` | H/V active for TX0 |
| RX_FRM0_BPC | `0x220854` | Color depth for TX0 |
| RX_INT_CLK | `0x200008` | Internal clock for frame rate calc |
| RX_PIXCLK_MULT | `0x220804` | Pixel clock multiplier |
| RX_PIXCLK_DIV | `0x220814` | Pixel clock divider |
| RX_ML_PHY_ERR_0–3 | `0x22011C`–`0x220128` | Per-lane DP PHY error counters |

**Frame rate calculation:**
```
intclk = RX_INT_CLK[25:16] * 10000
frame_rate = intclk * RX_PIXCLK_MULT[7:0] * 100 / RX_PIXCLK_DIV[31:0]
```

## Pre-Built Firmware Images

The repository includes multiple VXR7200 firmware versions in `vxr7200_firmware/`:

| File | Date | Size | Notes |
|------|------|------|-------|
| Beyond_v02_20230915.fullrom | 2023-09-15 | 512 KB | |
| Beyond_v03_20231221.fullrom | 2023-12-21 | 512 KB | Required for 2544x2544 @60Hz |
| BigScreenVR_v01_*.FullRom | Various | 512 KB | Earlier versions |
| BigScreenVR_v02_*.FullRom | Various | 512 KB | |

**Source files:** `src/Devices/vxr_interface.c/h`